欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP3C16Q240C8N 参数 Datasheet PDF下载

EP3C16Q240C8N图片预览
型号: EP3C16Q240C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 472.5MHz, 15408-Cell, CMOS, PQFP240, 34.60 X 34.60 MM, 4.10 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LEAD FREE, QFP-240]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL ]
 浏览型号EP3C16Q240C8N的Datasheet PDF文件第1页浏览型号EP3C16Q240C8N的Datasheet PDF文件第2页浏览型号EP3C16Q240C8N的Datasheet PDF文件第3页浏览型号EP3C16Q240C8N的Datasheet PDF文件第4页浏览型号EP3C16Q240C8N的Datasheet PDF文件第6页浏览型号EP3C16Q240C8N的Datasheet PDF文件第7页浏览型号EP3C16Q240C8N的Datasheet PDF文件第8页浏览型号EP3C16Q240C8N的Datasheet PDF文件第9页  
Chapter 1: Cyclone III Device Datasheet  
1–5  
Electrical Characteristics  
DC Characteristics  
This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT)  
tolerance, and bus hold specifications for Cyclone III devices.  
Supply Current  
Standby current is the current the device draws after the device is configured with no  
inputs or outputs toggling and no activity in the device. Use the Excel-based early  
power estimator (EPE) to get the supply current estimates for your design because  
these currents vary largely with the resources used. Table 1–4 lists I/O pin leakage  
current for Cyclone III devices.  
f
For more information about power estimation tools, refer to the PowerPlay Early Power  
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II  
Handbook.  
Table 1–4. Cyclone III Devices I/O Pin Leakage Current (1), (2)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max Unit  
II  
Input pin leakage current  
VI = 0 V to VCCIOMAX  
–10  
10  
A  
Tristated I/O pin leakage  
current  
IOZ  
VO = 0 V to VCCIOMAX  
–10  
10  
A  
Notes to Table 1–4:  
(1) This value is specified for normal device operation. The value varies during device power-up. This applies for all  
CCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V).  
V
(2) 10 A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the  
observed when the diode is on.  
Bus Hold  
Bus hold retains the last valid logic state after the source driving it either enters the  
high impedance state or is removed. Each I/O pin has an option to enable bus hold in  
user mode. Bus hold is always disabled in configuration mode.  
Table 1–5 lists bus hold specifications for Cyclone III devices.  
(1)  
Table 1–5. Cyclone III Devices Bus Hold Parameter (Part 1 of 2)  
V
CCIO (V)  
Parameter  
Condition  
1.2  
1.5  
1.8  
2.5  
3.0  
3.3  
Unit  
Min Max Min  
Max Min Max Min Max Min Max Min Max  
Bus-hold  
low,  
sustaining  
current  
VIN > VIL  
(maximum)  
8
12  
30  
50  
70  
70  
A  
A  
Bus-hold  
high,  
sustaining  
current  
VIN < VIL  
(minimum)  
–8  
–12  
–30  
–50  
–70  
–70  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
 复制成功!