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EP3C16Q240C8N 参数 Datasheet PDF下载

EP3C16Q240C8N图片预览
型号: EP3C16Q240C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 472.5MHz, 15408-Cell, CMOS, PQFP240, 34.60 X 34.60 MM, 4.10 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LEAD FREE, QFP-240]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL ]
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1–4  
Chapter 1: Cyclone III Device Datasheet  
Electrical Characteristics  
Recommended Operating Conditions  
This section lists the functional operation limits for AC and DC parameters for  
Cyclone III devices. The steady-state voltage and current values expected from  
Cyclone III devices are provided in Table 1–3. All supplies must be strictly monotonic  
without plateaus.  
(1), (2)  
Table 1–3. Cyclone III Devices Recommended Operating Conditions  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
(3)  
VCCINT  
Supply voltage for internal logic  
1.15  
1.2  
1.25  
V
Supply voltage for output buffers, 3.3-V  
operation  
3.135  
2.85  
3.3  
3
3.465  
3.15  
V
V
V
V
V
V
V
Supply voltage for output buffers, 3.0-V  
operation  
Supply voltage for output buffers, 2.5-V  
operation  
2.375  
1.71  
2.5  
1.8  
1.5  
1.2  
2.5  
2.625  
1.89  
(3), (4)  
VCCIO  
Supply voltage for output buffers, 1.8-V  
operation  
Supply voltage for output buffers, 1.5-V  
operation  
1.425  
1.14  
1.575  
1.26  
Supply voltage for output buffers, 1.2-V  
operation  
Supply (analog) voltage for PLL  
regulator  
(3)  
VCCA  
2.375  
2.625  
(3)  
VCCD_PLL  
Supply (digital) voltage for PLL  
Input voltage  
1.15  
–0.5  
0
1.2  
1.25  
3.6  
V
V
VI  
VO  
Output voltage  
VCCIO  
85  
V
For commercial use  
For industrial use  
For extended temperature  
For automotive use  
Standard power-on reset  
0
°C  
°C  
°C  
°C  
–40  
–40  
–40  
100  
125  
125  
TJ  
Operating junction temperature  
50 µs  
50 µs  
50 ms  
3 ms  
10  
(5)  
(POR)  
tRAMP  
Power supply ramp time  
(6)  
Fast POR  
Magnitude of DC current across  
PCI-clamp diode when enabled  
IDiode  
mA  
Notes to Table 1–3:  
(1) VCCIO for all I/O banks must be powered up during device operation. All VCCA pins must be powered to 2.5 V (even when PLLs are not used), and  
must be powered up and powered down at the same time.  
(2) VCCD_PLL must always be connected to VCCINT through a decoupling capacitor and ferrite bead.  
(3) The VCC must rise monotonically.  
(4) All input buffers are powered by the VCCIO supply.  
(5) POR time for Standard POR ranges between 50–200 ms. Each individual power supply should reach the recommended operating range within  
50 ms.  
(6) POR time for Fast POR ranges between 3–9 ms. Each individual power supply should reach the recommended operating range within 3 ms.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
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