1–32
Chapter 1: Cyclone III Device Datasheet
Document Revision History
Document Revision History
Table 1–40 lists the revision history for this document.
Table 1–40. Document Revision History (Part 1 of 3)
Date
July 2012
Version
Changes
3.5
Updated minimum fHSCLK value to 5 MHz.
■ Updated “Supply Current” on page 1–5 and “Periphery Performance” on page 1–17.
December 2011
3.4
■ Updated Table 1–3, Table 1–4, Table 1–13, Table 1–16, Table 1–17, Table 1–20, and
Table 1–25.
■ Removed Table 1-32 and Table 1-33.
■ Added Literature: External Memory Interfaces reference.
Minor changes to the text.
January 2010
3.3
December 2009
July 2009
3.2
3.1
Minor edit to the hyperlinks.
■ Changed chapter title from DC and Switching Characteristics to “Cyclone III Device Data
Sheet” on page 1–1.
■ Updated (Note 1) to Table 1–23 on page 1–17.
■ Updated “External Memory Interface Specifications” on page 1–23.
■ Replaced Table 1–32 on page 1–23.
June 2009
3.0
■ Replaced Table 1–33 on page 1–23.
■ Added Table 1–36 on page 1–26.
■ Updated “I/O Timing” on page 1–28.
■ Removed “Typical Design Performance” section.
■ Removed “I/O Timing” subsections.
■ Updated chapter to new template.
■ Updated Table 1–1, Table 1–3, and Table 1–18.
■ Added (Note 7) to Table 1–3.
October 2008
2.2
2.1
■ Added the “OCT Calibration Timing Specification” section.
■ Updated “Glossary” section.
■ Updated Table 1–38.
■ Added BLVDS information (I/O standard) into Table 1–39, Table 1–40, Table 1–41,
Table 1–42.
■ Updated Table 1–43, Table 1–46, Table 1–47, Table 1–48, Table 1–49, Table 1–50,
Table 1–51, Table 1–52, Table 1–53, Table 1–54, Table 1–55, Table 1–56, Table 1–57,
Table 1–58, Table 1–59, Table 1–60, Table 1–61, Table 1–62, Table 1–63, Table 1–68,
Table 1–69, Table 1–74, Table 1–75, Table 1–80, Table 1–81, Table 1–86, Table 1–87,
Table 1–92, Table 1–93, Table 1–94, Table 1–95, Table 1–96, Table 1–97, Table 1–98, and
Table 1–99.
July 2008
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
INTEL [ INTEL ]
