Duty Cycle Distortion
Table 5–86. Maximum DCD for DDIO Output on Row I/O Pins with PLL in the
Clock Path (Part 2 of 2)
Note (1)
Maximum DCD (PLL Output Clock Feeding
DDIO Clock Port)
Row DDIO Output I/O
Standard
Unit
-3 Device
-4 & -5 Device
LVDS/ HyperTransport
technology
180
180
ps
Note to Table 5–86:
(1) The DCD specification is based on a no logic array noise condition.
Table 5–87. Maximum DCD for DDIO Output on Column I/O with PLL in the
Clock Path Note (1)
Maximum DCD (PLL Output Clock Feeding
DDIO Clock Port)
Column DDIO Output I/O
Standard
Unit
-3 Device
-4 & -5 Device
3.3-V LVTTL
145
100
85
160
110
95
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVCMOS
2.5V
1.8V
85
100
155
75
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
140
65
60
70
50
65
70
80
60
70
60
70
55
70
85
100
-
155
180
LVPECL
180
Notes to Table 5–87:
(1) The DCD specification is based on a no logic array noise condition.
(2) 1.2-V HSTL is only supported in -3 devices.
5–86
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
INTEL [ INTEL ]
