Timing Model
Figure 5–6. Measurement Setup for tzx
t
, Tristate to Driving High
ZX
Disable Enable
½ V
CCINT
OE
Din
OE
Din
Dout
“1”
1 MΩ
t
Dout
zh
½ V
CCIO
t
, Tristate to Driving Low
ZX
Disable Enable
½ V
CCINT
OE
Din
1 MΩ
Dout
OE
Din
“0”
½ V
t
CCIO
zl
Dout
Table 5–35 specifies the input timing measurement setup.
Table 5–35. Timing Measurement Methodology for Input Pins (Part 1 of 2)
Notes (1)–(4)
Measurement Conditions
I/O Standard
Measurement Point
VMEAS (V)
VCCIO (V)
VREF (V)
Edge Rate (ns)
LVTTL (5)
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
1.5675
1.5675
1.1875
0.855
0.7125
1.485
1.485
1.1625
1.1625
0.83
LVCMOS (5)
2.5 V (5)
1.8 V (5)
1.5 V (5)
PCI (6)
PCI-X (6)
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.163
1.163
0.830
0.830
0.830
0.83
0.83
5–26
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
INTEL [ INTEL ]
