Operating Conditions
Table 5–30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 2 of 2)
Notes (1), 2
Resistance Tolerance
Symbol
Description
Conditions
Commercial
Max
Industrial
Max
Unit
50-Ω RS Internal series termination with
calibration (50-Ω setting)
VCCIO = 3.3/2.5 V
5
10
30
30
10
30
10
30
15
10
36
15
10
50
15
%
3.3/2.5
Internal series termination without VCCIO = 3.3/2.5 V
calibration (50-Ω setting)
30
30
5
%
%
%
%
%
%
%
%
%
%
%
%
%
50-Ω RT Internal parallel termination with
calibration (50-Ω setting)
VCCIO = 1.8 V
VCCIO = 1.8 V
2.5
25-Ω RS Internal series termination with
calibration (25-Ω setting)
1.8
Internal series termination without VCCIO = 1.8 V
calibration (25-Ω setting)
30
5
50-Ω RS Internal series termination with
calibration (50-Ω setting)
VCCIO = 1.8 V
1.8
Internal series termination without VCCIO = 1.8 V
calibration (50-Ω setting)
30
10
8
50-Ω RT Internal parallel termination with
calibration (50-Ω setting)
VCCIO = 1.8 V
VCCIO = 1.5 V
1.8
50−Ω RS Internal series termination with
calibration (50-Ω setting)
1.5
Internal series termination without VCCIO = 1.5 V
calibration (50-Ω setting)
36
10
8
50-Ω RT Internal parallel termination with
calibration (50-Ω setting)
VCCIO = 1.5 V
VCCIO = 1.2 V
1.5
50−Ω RS Internal series termination with
calibration (50-Ω setting)
1.2
Internal series termination without VCCIO = 1.2 V
calibration (50-Ω setting)
50
10
50-Ω RT Internal parallel termination with
calibration (50-Ω setting)
VCCIO = 1.2 V
1.2
Notes for Table 5–30:
(1) The resistance tolerances for calibrated SOCT and POCT are for the moment of calibration. If the temperature or
voltage changes over time, the tolerance may also change.
(2) On-chip parallel termination with calibration is only supported for input pins.
5–18
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
INTEL [ INTEL ]
