Stratix II Architecture
Figure 2–28. DSP Block Diagram for 18 × 18-Bit Configuration
Optional Serial Shift
Register Inputs from
Previous DSP Block
Output
Selection
Adder Output Block
Multiplier Block
PRN
PRN
D
Multiplexer
Q
ENA
CLRN
D
Q
Q1.15
Round/
Saturate
Optional Stage Configurable
as Accumulator or Dynamic
Adder/Subtractor
ENA
CLRN
PRN
From the row
interface block
D
Q
ENA
CLRN
Adder/
Q1.15
Subtractor/
Round/
Accumulator
Saturate
1
PRN
D
Q
PRN
ENA
CLRN
D
Q
Q1.15
Round/
Saturate
ENA
CLRN
PRN
D
Q
Summation
Block
ENA
CLRN
Adder
D
Q
ENA
CLRN
PRN
D
Q
PRN
ENA
CLRN
D
Q
Q1.15
Round/
Saturate
Summation Stage
for Adding Four
ENA
CLRN
PRN
Multipliers Together
D
Q
ENA
CLRN
Adder/
Subtractor/
Accumulator
2
Q1.15
Round/
Saturate
PRN
D
Q
PRN
ENA
CLRN
D
Q
Q1.15
Round/
Saturate
Optional Serial Shift
Register Outputs to
Next DSP Block
ENA
CLRN
Optional Pipline
Register Stage
PRN
D
Q
in the Column
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
ENA
CLRN
to MultiTrack
Interconnect
Altera Corporation
May 2007
2–43
Stratix II Device Handbook, Volume 1
INTEL [ INTEL ]
