Stratix II Architecture
Figure 2–15. Register Chain within an LAB Note (1)
From Previous ALM
Within The LAB
reg_chain_in
To general or
local routing
To general or
local routing
adder0
D
Q
reg0
Combinational
Logic
To general or
local routing
adder1
D
Q
reg1
To general or
local routing
To general or
local routing
To general or
local routing
adder0
D
Q
reg0
Combinational
Logic
To general or
local routing
adder1
D
Q
reg1
To general or
local routing
reg_chain_out
To Next ALM
within the LAB
Note to Figure 2–15:
(1) The combinational or adder logic can be utilized to implement an unrelated, un-registered function.
See the “MultiTrack Interconnect” on page 2–22 section for more
information on register chain interconnect.
Altera Corporation
May 2007
2–21
Stratix II Device Handbook, Volume 1
INTEL [ INTEL ]
