ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 14. Maximum DMA Acknowledge Delay Register Values (Sheet 2 of 2)
Maximum DMA Acknowledge Delay
(25-MHz internal clock and default Setup timing)
Register Value
E0h
10h
90h
50h
D0h
30h
B0h
13 clocks = 520 ns
14 clocks = 560 ns
15 clocks = 600 ns
16 clocks = 640 ns
17 clocks = 680 ns
18 clocks = 720 ns
19 clocks = 760 ns
10.7.4
External Data (PD6722 only, Socket A, Index 2Fh)
Register Name: External Data
Index: 2Fh only
Register Per: socket
Extended Index: 0Ah
Bit 4 Bit 3
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
External Data External Data External Data External Data External Data External Data External Data External Data
7
6
5
4
3
2
1
0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
RW:0
Bits 7:0 — External Data
This register is updated and accessed according to the setting of bits 3 and 4 of the Socket A
Extension Control 2 register (Index 2Fh, Extended Index 0Bh).
Table 15. Functions of Socket A External Data Register
Socket A Extension Control 2
Function of Socket A External Data Register
Bit 4: GPSTB
on IOW*
Bit 3: GPSTB
on IOR*
0
0
0
1
Scratchpad
External read port: A_GPSTB is a read buffer enable for external data on
SD[15:8]
External write port: A_GPSTB is a write latch enable for SD[15:8] to get
latched to an external register. Reads of Socket A External Data register
produce the value written to the latch.
1
1
0
1
Reserved
Note: For software compatibility of external data access accross the PC Card (PCMCIA) controller
product line, the Socket A External Data register should only be used as a write port and not as a
read port. Also for compatibility, only the lower nibble of External Data should be accessed and
the upper nibble should be ignored.
Refer to “Using GPSTB Pins for External Port Control (PD6722 only)” on page 91 for more
information on the use of the External Data register.
Datasheet
81
INTEL [ INTEL ]
