MCS@ 51 CONTROLLER
PACKAGES
Part
8051AH
8031AH
8052AH
8032AH
6752BH*
8751H
8751 H-8
8051AHP
8751 BH
Prefix
P
D
N
Package Type
40-Pin Plastic DIP
40-Pin CERDIP
44-Pin PLCC
‘ja
Ojc
45°chV
4!5”CIW
46°C/W
16“C/W
15“CAIV
18°CfW
D
P
D
P
N
40-Pin CERDIP
40-Pin Plastic DIP
40-Pin CERDIP
40-Pin Plastic DIP
44-Pin PLCC
45”CIW
45”CIW
45°c/w
36”CIW
47”C1W
45“CIW
16°CfW
15“cf w
12°cf w
16”Cf W
NOTE:
*8752BH
is
36”/10” for D, and 38”/22” for N.
All thermal impedance data is approximate for static air conditions at IW of power dissipation. Values will
change depending on operating conditions and application. See the Intel Pac/raging
Handbook
(Order Number
240800) for a description of Intel’s thermal impedance test methodology.
~“52’80320NL’
L{
~
40
39
38
37
36
35
34
33
Vcc
P’,’ ADO
PO.1 AD1
PO.2 A02
PO.3 A03
PO.4 AD4
PO.5 AD5
P06 AD’
3 PO.7A07
3
EIJvpp”
Z
ALEIPROG”
3%FFI
3 P2.7 A15
2 P2.6A14
3 P2.5 A13
I P2.4 A12
1 P2.3 Al 1
> P2.2 AlO
3 P2 1 A9
X P20 A8
T2
T2EX
‘1
‘ss
+!--
29
26
27
26
25
24
23
22
21
EPROM only
q
“*Do
not connect
PI.’
P1.1
P1.2
P1.3
P1.4
P1.5
P1,6
P1.7
RST
RU2 P3.O
TXD P3.1
INTO P3.2
INT1 P3,3
TOP3 4
11 P3.5
~ P3.6
t% P3.7
XTAL2
XTAL1
I’__”ll
1
2
3
4
5
6
7
6
9
10
11
12
13
14
15
16
17
16
19
PI.6 ::8:;
P*,7 .:,.:
RST io;
(Rxo) P3.O :ji:
.1:;
:ji;
:!;;
:j:;
fTo) P3.4 :>!:
neaslvsd**
fTXD) P3.1
(INTo) P3.2
(INT1) P3.3
8X5X
272318-2
DIP
reserved
pins.
PLCC
Figure 2. MCS@51 Controller Connections
3
INTEL [ INTEL CORPORATION ]
