Networking Silicon — 82551IT
The 82551IT supports PCI interface standards. In the PCI mode, it is five volts tolerant and
supports both 5 V and 3.3 V signaling environments.
Table 47. PCI Interface DC Specifications
Symbol
VIHP
Parameter
Condition
Min
Max
Units
Notes
Input High Voltage
Input Low Voltage
0.475VCC VIO + 0.5
V
V
VILP
-0.5
0.325VCC
VIPUP
VIPDP
IILP
Input Pull-up Voltage
Input Pull-down Voltage
0.7VCC
V
1
1
2
0.2VCC
±10
V
Input Leakage Current 0 < VIN < VCC
µA
Iout = -2 mA
2.4
V
V
VOHP
Output High Voltage
PCI
I
out = -500 µA
Iout = 3 mA, 6 mA
out = 1500 µA
0.9VCC
0.55
V
V
VOLP
Output Low Voltage
3, PCI
I
0.1VCC
CINP
Input Pin Capacitance
CLK Pin Capacitance
IDSEL Pin Capacitance
Pin Inductance
10
12
8
pF
pF
pF
nH
4
4
4
4
CCLKP
CIDSEL
LPINP
5
20
PME# Input Leakage
Current
IOFFPME
VO < VIO
1
mA
5
NOTES:
1. These values are only applicable in 3.3 V signaling environments. Outside of this limit the input buffer must
consume its minimum current.
2. Input leakage currents include high-Z output leakage for all bidirectional buffers with tristate outputs.
3. Signals without pull-up resistors have 3 mA low output current; and signals requiring pull-up resistors, 6 mA.
The signals requiring pull-up resistors include: FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR# and
PERR#.
4. This value is characterized but not tested.
5. This input leakage current is the maximum allowable leakage into the PME# open drain driver when power is
removed from VCC of the component. This assumes that no event has occurred to cause the device to
assertion of PME#.
Table 48. Flash/EEPROM Interface DC Specifications
Symbol
Parameter
Condition
Min
Max
Units
Notes
VIHL
VILL
Input High Voltage
Input Low Voltage
2.0
VCC + 0.5
0.8
V
V
-0.5
Input Low Leakage
Current
IILL
0 < VIN < VCC
±20
µA
VOHL
VOLL
CINL
Output High Voltage
Output Low Voltage
Input Pin Capacitance
Iout = -1 mA
Iout = 2 mA
2.4
V
V
0.4
10
pF
1
1. This value is characterized but not tested.
Datasheet
77
INTEL [ INTEL ]
