Networking Silicon — 82551IT
The Statistical Counters are initially set to zero by the 82551IT after reset. They cannot be preset to
anything other than zero. The 82551IT increments the counters by internally reading them,
incrementing them and writing them back. This process is invisible to the CPU and PCI bus. In
addition, the counters adhere to the following rules:
• The counters are wrap-around counters. After reaching FFFFFFFFh the counters wrap around
to 0.
• The 82551IT updates the required counters for each frame. It is possible for more than one
counter to be updated as multiple errors can occur in a single frame.
• The counters are 32 bits wide and their behavior is fully compatible with the IEEE 802.1
standard. The 82551IT supports all mandatory and recommend statistics functions through the
status of the receive header and directly through these Statistical Counters.
The CPU can access the counters by issuing a Dump Statistical Counters SCB command. This
provides a “snapshot”, in main memory, of the internal 82551IT statistical counters. The 82551IT
supports 19 counters. The dump could consist of either 16 or 19 counters, depending on the status
of the Extended Statistics Counters configuration bits in the Configuration command.
Datasheet
59
INTEL [ INTEL ]
