82551IT — Networking Silicon
5.3.2.2
Link Status Change Event
The 82551IT link status indication circuit is capable of issuing a PME on a link status change from
a valid link to an invalid link condition or vice versa. The 82551IT reports a PME link status event
in all power states. The PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA
Configure command.
5.4
Parallel Flash
The 82551IT’s parallel interface is used for a Flash interface. The 82551IT supports a glueless
interface to an 8-bit wide, 128 KB, parallel memory device.
The Flash (or boot PROM) is read from or written to whenever the host CPU performs a read or a
write operation to a memory location that is within the Flash mapping window. All accesses to the
Flash, except read accesses, require the appropriate command sequence for the device used. (Refer
to the specific Flash data sheet for more details on reading from or writing to the Flash device.) The
accesses to the Flash are based on a direct decode of CPU accesses to a memory window defined in
either the 82551IT Flash Base Address Register (PCI Configuration space at offset 18h) or the
Expansion ROM Base Address Register (PCI Configuration space at offset 30h). The 82551IT
asserts control to the Flash when it decodes a valid access.
The 82551IT supports an external Flash memory (or boot PROM) of up to 128 KB. The Expansion
ROM address can be separately disabled by setting the corresponding bit in the EEPROM, word
Ah.
Note: Flash accesses must always be assembled or disassembled by the 82551IT whenever the access is
greater than a byte-wide access. Due to slow access times to a typical Flash and to avoid violating
PCI bus holding specifications (no more than 16 wait states inserted for any cycles that are not
system initiation cycles), the maximum data size is either one word or one byte for a read operation
and one byte only for a write operation.
5.5
Serial EEPROM Interface
The serial EEPROM stores configuration data for the 82551IT and is a serial in/serial out device.
The 82551IT supports either a 64-register or 256-register size EEPROM and automatically detects
the EEPROM’s size. The EEPROM should also operate at a frequency of at least 1 MHz.
30
Datasheet
INTEL [ INTEL ]
