80C186EC/188EC, 80L186EC/188EC
Table 2. Pin Descriptions (Continued)
Output
Pin
Input
Type
Pin Name
Pin Description
Type
States
RD
O
Ð
H(Z)
R(Z)
I(1)
ReaD output signals that the accessed memory or I/O
device should drive data information onto the data bus.
P(1)
WR
O
Ð
H(Z)
R(Z)
I(1)
WRite output signals that data available on the data bus are
to be written into the accessed memory or I/O device.
P(1)
READY
DEN
I
A(L)
S(L)
Ð
READY input to signal the completion of a bus cycle. READY
must be active to terminate any 80C186EC bus cycle, unless
it is ignored by correctly programming the Chip-Select unit.
(Note 1)
O
Ð
H(Z)
R(Z)
I(1)
Data ENable output to control the enable of bi-directional
transceivers in a buffered system. DEN is active only when
data is to be transferred on the bus.
P(1)
DT/R
LOCK
O
Ð
H(Z)
R(Z)
I(X)
Data Transmit/Receive output controls the direction of a bi-
directional buffer in a buffered system.
P(X)
I/O
A(L)
H(Z)
R(Z)
I(X)
LOCK output indicates that the bus cycle in progress is not
interruptable. The processor will not service other bus
requests (such as HOLD) while LOCK is active. This pin is
configured as a weakly held high input while RESIN is active
and must not be driven low.
P(X)
HOLD
HLDA
I
A(L)
Ð
Ð
HOLD request input to signal that an external bus master
wishes to gain control of the local bus. The processor will
relinquish control of the local bus between instruction
boundaries that are not LOCKed.
O
H(1)
R(0)
I(0)
HoLD Acknowledge output to indicate that the processor
has relinquished control of the local bus. When HLDA is
asserted, the processor will (or has) floated its data bus and
control signals allowing another bus master to drive the
signals directly.
P(0)
NCS
O
I
Ð
H(1)
R(1)
I(1)
Numerics Coprocessor Select output is generated when
acessing a numerics coprocessor. This signal does not exist
on the 80C188EC/80L188EC.
P(1)
ERROR
A(L)
Ð
ERROR input that indicates the last numerics processor
extension operation resulted in an exception condition. An
interrupt TYPE 16 is generated if ERROR is sampled active
at the beginning of a numerics operation. Systems not using
an 80C187 must tie ERROR to V . This signal does not
CC
exist on the 80C188EC/80L188EC.
NOTE:
Pin names in parentheses apply to the 80C188EC/80L188EC.
12
INTEL [ INTEL ]
