80C186EC 188EC 80L186EC 188EC
PCB
Offset
00H
02H
04H
06H
08H
0AH
0CH
0EH
10H
12H
14H
16H
18H
1AH
1CH
1EH
20H
22H
24H
26H
28H
2AH
2CH
2EH
30H
32H
34H
46H
38H
3AH
3CH
3EH
Function
Master PIC Port 0
Master PIC Port 1
Slave PIC Port 0
Slave PIC Port 1
Reserved
SCU Int Req Ltch
DMA Int Req Ltch
TCU Int Req Ltch
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
WDT Reload High
WDT Reload Low
WDT Count High
WDT Count Low
WDT Clear
WDT Disable
Reserved
Reserved
T0 Count
T0 Compare A
T0 Compare B
T0 Control
T1 Count
T1 Compare A
T1 Compare B
T1 Control
PCB
Offset
40H
42H
44H
46H
48H
4AH
4CH
4EH
50H
52H
54H
56H
58H
5AH
5CH
5EH
60H
62H
64H
66H
68H
6AH
6CH
6EH
70H
72H
74H
76H
78H
7AH
7CH
7EH
Function
T2 Count
T2 Compare
Reserved
T2 Control
Port 3 Direction
Port 3 Pin State
Port 3 Mux Control
Port 3 Data Latch
Port 1 Direction
Port 1 Pin State
Port 1 Mux Control
Port 1 Data Latch
Port 2 Direction
Port 2 Pin State
Port 2 Mux Control
Port 2 Data Latch
SCU 0 Baud
SCU 0 Count
SCU 0 Control
SCU 0 Status
SCU 0 RBUF
SCU 0 TBUF
Reserved
Reserved
SCU 1 Baud
SCU 1 Count
SCU 1 Control
SCU 1 Status
SCU 1 RBUF
SCU 1 TBUF
Reserved
Reserved
PCB
Offset
80H
82H
84H
86H
88H
8AH
8CH
8EH
90H
92H
94H
96H
98H
9AH
9CH
9EH
A0H
A2H
A4H
A6H
A8H
AAH
ACH
AEH
B0H
B2H
B4H
B6H
B8H
BAH
BCH
BEH
Function
GCS0 Start
GCS0 Stop
GCS1 Start
GCS1 Stop
GCS2 Start
GCS2 Stop
GCS3 Start
GCS3 Stop
GCS4 Start
GCS4 Stop
GCS5 Start
GCS5 Stop
GCS6 Start
GCS6 Stop
GCS7 Start
GCS7 Stop
LCS Start
LCS Stop
UCS Start
UCS Stop
Relocation Register
Reserved
Reserved
Reserved
Refresh Base Addr
Refresh Time
Refresh Control
Refresh Address
Power Control
Reserved
Step ID
Powersave
PCB
Offset
C0H
C2H
C4H
C6H
C8H
CAH
CCH
CEH
D0H
D2H
D4H
D6H
D8H
DAH
DCH
DEH
E0H
E2H
E4H
E6H
E8H
EAH
ECH
EEH
F0H
F2H
F4H
F6H
F8H
FAH
FCH
FEH
Function
DMA 0 Source Low
DMA 0 Source High
DMA 0 Dest Low
DMA 0 Dest High
DMA 0 Count
DMA 0 Control
DMA Module Pri
DMA Halt
DMA 1 Source Low
DMA 1 Source High
DMA 1 Dest Low
DMA 1 Dest High
DMA 1 Count
DMA 1 Control
Reserved
Reserved
DMA 2 Source Low
DMA 2 Source High
DMA 2 Dest Low
DMA 2 Dest High
DMA 2 Count
DMA 2 Control
Reserved
Reserved
DMA 3 Source Low
DMA 3 Source High
DMA 3 Dest Low
DMA 3 Dest High
DMA 3 Count
DMA 3 Control
Reserved
Reserved
Figure 3 Peripheral Control Block Registers
6
INTEL [ INTEL CORPORATION ]
