80C186EC/188EC, 80L186EC/188EC
Table 2. Pin Descriptions (Continued)
Pin
Input
Type
Output
States
Pin Name
Pin Description
Type
PEREQ
I
A(L)
Ð
Processor Extension REQuest signals that a data
transfer between an 80C187 Numerics Processor
Extension and Memory is pending. Systems not using an
80C187 must tie this pin to V . This signal does not exist
SS
on the 80C188EC/80L188EC.
UCS
LCS
O
Ð
H(1)
R(1)
I(1)
Upper Chip Select will go active whenever the address of
a memory or I/O bus cycle is within the address range
programmed by the user. After reset, UCS is configured to
be active for memory accesses between 0FFC00H and
0FFFFFH.
P(1)
O
O
Ð
Ð
H(1)
R(1)
I(1)
Lower Chip Select will go active whenever the address of
a memory or I/O bus cycle is within the address range
programmed by the user. LCS is inactive after a reset.
P(1)
P1.0/GCS0
P1.1/GCS1
P1.2/GCS2
P1.3/GCS3
P1.4/GCS4
P1.5/GCS5
P1.6/GCS6
P1.7/GCS7
H(X)/H(1)
R(1)
These pins provide a multiplexed function. If enabled,
each pin can provide a General purpose Chip Select
output which will go active whenever the address of a
memory or I/O bus cycle is within the address limitations
programmed by the user. When not programmed as a
Chip-Select, each pin may be used as a general purpose
output port.
I(X)/I(1)
P(X)/P(1)
T0OUT
T1OUT
O
Ð
H(Q)
R(1)
I(Q)
Timer OUTput pins can be programmed to provide single
clock or continuous waveform generation, depending on
the timer mode selected.
P(X)
T0IN
T1IN
I
I
A(L)
A(E)
Ð
Timer INput is used either as clock or control signals,
depending on the timer mode selected. This pin may be
either level or edge sensitive depending on the
programming mode.
INT7:0
INTA
A(L)
A(E)
Ð
Maskable INTerrupt input will cause a vector to a specific
Type interrupt routine. The INT6:0 pins can be used as
cascade inputs from slave 8259A devices. The INT pins
can be configured as level or edge sensitive.
O
Ð
A(L)
Ð
H(1)
R(1)
I(1)
INTerrupt Acknowledge output is a handshaking signal
used by external 82C59A Programmable Interrupt
Controllers.
P(1)
P3.5
P3.4
I/O
O
H(X)
R(Z)
I(X)
Bidirectional, open-drain port pins.
H(X)
P3.3/DMAI1
P3.2/DMAI0
H(X)
R(0)
I(Q)
DMA Interrupt output goes active to indicate that the
channel has completed a transfer. DMAI1 and DMAI0 are
multiplexed with output only port functions.
P(X)
NOTE:
Pin names in parentheses apply to the 80C188EC/80L188EC.
13
INTEL [ INTEL ]
