80C186EC/188EC, 80L186EC/188EC
bus signals to CLKOUT. These figures along with
the information present in AC Specifications allow
the user to determine all the critical timing analysis
needed for a given application.
BUS CYCLE WAVEFORMS
Figures 18 through 24 present the various bus cy-
cles that are generated by the processor. What is
shown in the figure is the relationship of the various
272434–17
Pin names in parentheses apply to 80C188EC/80L188EC.
Figure 18. Memory Read, I/O Read, Instruction Fetch and Refresh Waveforms
43