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80C188EC13 参数 Datasheet PDF下载

80C188EC13图片预览
型号: 80C188EC13
PDF下载: 下载PDF文件 查看货源
内容描述: 16位高集成嵌入式处理器 [16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS]
分类和应用:
文件页数/大小: 57 页 / 787 K
品牌: INTEL [ INTEL ]
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80C186EC/188EC, 80L186EC/188EC  
Table 2. Pin Descriptions (Continued)  
Output  
Pin  
Input  
Type  
Pin Name  
Pin Description  
Type  
States  
P3.1/TXI1  
O
Ð
H(X)/H(Q)  
R(0)  
I(Q)  
Transmit Interrupt output goes active to indicate that  
serial channel 1 has completed a transfer. TXI1 is  
multiplexed with an output only Port function.  
P(X)  
P3.0/RXI1  
WDTOUT  
O
Ð
H(X)/H(Q)  
R(0)  
I(Q)  
Receive Interrupt output goes active to indicate that  
serial channel 1 has completed a reception. RXI1 is  
multiplexed with an output only port function.  
P(X)  
O
Ð
H(Q)  
R(1)  
I(Q)  
WatchDog Timer OUTput is driven low for four clock  
cycles when the watchdog timer reaches zero. WDTOUT  
may be ANDed with the power-on reset signal to reset the  
processor when the watchdog timer is not properly reset.  
P(X)  
P2.7/CTS1  
P2.3/CTS0  
I/O  
I/O  
A(L)  
H(X)  
R(Z)  
I(X)  
Clear-To-Send input is used to prevent the transmission  
of serial data on the TXD signal pin. CTS1 and CTS0 are  
multiplexed with an I/O Port function.  
P(X)  
P2.6/BCLK1  
P2.2/BCLK0  
A(L)/  
A(E)  
H(X)  
R(Z)  
I(X)  
Baud CLocK input can be used as an alternate clock  
source for each of the integrated serial channels. The  
BCLK inputs are multiplexed with I/O Port functions. The  
BCLK input frequency cannot exceed (/2 the operating  
frequency of the processor .  
P(X)  
P2.5/TXD1  
P2.1/TXD0  
I/O  
I/O  
A(L)  
A(L)  
H(Q)  
R(Z)  
Transmit Data output provides serial data information.  
The TXD outputs are multiplexed with I/O Port functions.  
During synchronous serial communications, TXD will  
function as a clock output.  
I(X)/I(Q)  
P(X)  
P2.4/RXD1  
P2.0/RXD0  
H(X)/H(Q)  
R(Z)  
Receive Data input accepts serial data information. The  
RXD pins are multiplexed with I/O Port functions. During  
synchronous serial communications, RXD is bi-directional  
and will become an output for transmission of data (TXD  
becomes the clock).  
I(X)/I(Q)  
P(X)  
DRQ3:0  
I
A(L)  
Ð
DMA ReQuest input pins are used to request a DMA  
transfer. The timing of the request is dependent on the  
programmed synchronization mode.  
NOTES:  
1. READY is A(E) for the rising edge of CLKOUT, S(E) for the falling edge of CLKOUT.  
2. Pin names in parentheses apply to the 80C188EC/80L188EC.  
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