80C187
CONTROL WORD
The NPX provides several processing options that are selected by loading a control word from memory into
the control register Figure 5 shows the format and encoding of fields in the control word
Table 2 Condition Code Interpretation
Instruction
FPREM FPREM1
(See Table 3)
C0(S)
C3(Z)
C1(A)
C2(C)
Reduction
0
e
Complete
1
e
Incomplete
Three Least Significant
Bits of Quotient
Q2
Q0
Q1
or O U
Zero or
O U
FCOM FCOMP
FCOMPP FTST
FUCOM FUCOMP
FUCOMPP FICOM
FICOMP
FXAM
FCHS FABS FXCH
FINCSTP FDECSTP
Constant Loads
FXTRACT FLD
FILD FBLD
FSTP (Ext Real)
FIST FBSTP
FRNDINT FST
FSTP FADD FMUL
FDIV FDIVR
FSUB FSUBR
FSCALE FSQRT
FPATAN F2XM1
FYL2X FYL2XP1
FPTAN FSIN
FCOS FSINCOS
Result of Comparison
(See Table 4)
Operand is not
Comparable (Table 4)
Operand Class
(See Table 5)
Sign
or O U
Operand Class
(Table 5)
UNDEFINED
Zero
or O U
UNDEFINED
UNDEFINED
Roundup
or O U
UNDEFINED
UNDEFINED
Roundup
or O U
Undefined
if C2
e
1
Reduction
0
e
Complete
1
e
Incomplete
FLDENV FRSTOR
FLDCW FSTENV
FSTCW FSTSW
FCLEX FINIT
FSAVE
O U
Each Bit Loaded from Memory
UNDEFINED
When both IE and SF bits of status word are set indicating a stack exception this bit distinguishes between
stack overflow (C1
e
1) and underflow (C1
e
0)
Reduction
If FPREM or FPREM1 produces a remainder that is less than the modulus reduction is complete When
reduction is incomplete the value at the top of the stack is a partial remainder which can be used as input to
further reduction For FPTAN FSIN FCOS and FSINCOS the reduction bit is set if the operand at the top of
the stack is too large In this case the original operand remains at the top of the stack
Roundup
When the PE bit of the status word is set this bit indicates whether one was added to the least significant bit of
the result during the last rounding
UNDEFINED Do not rely on finding any specific value in these bits
7
INTEL [ INTEL CORPORATION ]
