80C186EC/188EC, 80L186EC/188EC
Table 2. Pin Descriptions
Output
States
Pin
Type
Input
Type
Pin Name
Pin Description
a
POWER 5V 10% power supply connection
g
V
V
P
G
I
Ð
Ð
Ð
CC
SS
Ð
GROUND
CLKIN
A(E)
Ð
CLocK INput is the external clock input. An external
oscillator operating at two times the required processor
operating frequency can be connected to CLKIN. For
crystal operation, CLKIN (along with OSCOUT) are the
crystal connections to an internal Pierce oscillator.
OSCOUT
O
Ð
H(Q)
R(Q)
I(Q)
OSCillator OUTput is only used when using a crystal to
generate the internal clock. OSCOUT (along with CLKIN)
are the crystal connections to an internal Pierce oscillator.
This pin can not be used as 2X clock output for non-
crystal applications (i.e. this pin is not connected for non-
crystal applications).
P(X)
CLKOUT
RESIN
O
I
Ð
H(Q)
R(Q)
I(Q)
CLocK OUTput provides a timing reference for inputs and
outputs of the processor, and is one-half the input clock
(CLKIN) frequency. CLKOUT has a 50% duty cycle and
transitions every falling edge of CLKIN.
P(X)
A(L)
Ð
RESet IN causes the processor to immediately terminate
any bus cycle in progress and assume an initialized state.
All pins will be driven to a known state, and RESOUT will
also be driven active. The rising edge (low-to-high)
transition synchronizes CLKOUT with CLKIN before the
processor begins fetching opcodes at memory location
0FFFF0H.
RESOUT
PDTMR
O
Ð
H(0)
R(1)
I(0)
RESet OUTput that indicates the processor is currently in
the reset state. RESOUT will remain active as long as
RESIN remains active.
P(0)
I/O
A(L)
H(WH)
R(Z)
P(WH)
I(WH)
Power-Down TiMeR pin (normally connected to an
external capacitor) that determines the amount of time the
processors waits after an exit from Powerdown before
resuming normal operation. The duration of time required
will depend on the startup characteristics of the crystal
oscillator.
NMI
I
I
A(E)
A(E)
Ð
Ð
Non-Maskable Interrupt input causes a TYPE-2 interrupt
to be serviced by the CPU. NMI is latched internally.
TEST/BUSY
(TEST)
TEST is used during the execution of the WAIT instruction
to suspend CPU operation until the pin is sampled active
(LOW). TEST is alternately known as BUSY when
interfacing with an 80C187 numerics coprocessor
(80C186EC only).
A19/S6/ONCE
I/O
A(L)
H(Z)
R(WH)
I(0)
This pin drives address bit 19 during the address phase of
the bus cycle. During T2 and T3 this pin functions as
status bit 6. S6 is low to indicate CPU bus cycles and high
to indicate DMA or refresh bus cycles. During a processor
reset (RESIN active) this pin becomes the ONCE input
pin. Holding this pin low during reset will force the part into
ONCE Mode.
P(0)
NOTE:
Pin names in parentheses apply to the 80C188EC/80L188EC.
10
INTEL [ INTEL ]
