80C186XL 80C188XL
16-Bit High-Integration Embedded Processors
CONTENTS
INTRODUCTION
80C186XL CORE ARCHITECTURE
80C186XL Clock Generator
Bus Interface Unit
80C186XL PERIPHERAL
ARCHITECTURE
Chip-Select Ready Generation Logic
DMA Unit
Timer Counter Unit
Interrupt Control Unit
Enhanced Mode Operation
Queue-Status Mode
DRAM Refresh Control Unit
Power-Save Control
Interface for 80C187 Math Coprocessor
(80C186XL Only)
ONCE Test Mode
PACKAGE INFORMATION
Pin Descriptions
80C186XL 80C188XL Pinout
Diagrams
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
DC SPECIFICATIONS
Power Supply Current
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CONTENTS
AC SPECIFICATIONS
Major Cycle Timings (Read Cycle)
Major Cycle Timings (Write Cycle)
Major Cycle Timings (Interrupt
Acknowledge Cycle)
Software Halt Cycle Timings
Clock Timings
Ready Peripheral and Queue Status
Timings
Reset and Hold HLDA Timings
AC TIMING WAVEFORMS
AC CHARACTERISTICS
EXPLANATION OF THE AC
SYMBOLS
DERATING CURVES
80C186XL 80C188XL EXPRESS
80C186XL 80C188XL EXECUTION
TIMINGS
INSTRUCTION SET SUMMARY
REVISION HISTORY
ERRATA
PRODUCT IDENTIFICATION
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INTEL [ INTEL CORPORATION ]
