80960JA/JF/JD/JT 3.3 V Microprocessor
1.0
Introduction
This document contains information for the 80960Jx microprocessor, including electrical
characteristics and package pinout information. Detailed functional descriptions — other than
parametric performance — are published in the
i960
®
Jx Microprocessor Developer’s Manual
(272483).
Figure 1.
80960Jx Microprocessor Package Options
i
A80960JX
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M
© 19xx
i960
®
i
GD80960JX
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M
© 19xx
i
132-Pin PGA
NG80960JX
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M
© 19xx
136-Ball MPBGA
132-Pin PQFP
Throughout this data sheet, references to “80960Jx” indicate features that apply to all of the
following:
•
80960JA — 3.3 V (5 V Tolerant), 2 Kbyte instruction cache, 1 Kbyte data cache
•
80960JF — 3.3 V (5 V Tolerant), 4 Kbyte instruction cache, 2 Kbyte data cache
•
80960JD — 3.3 V (5 V Tolerant), 4 Kbyte instruction cache, 2 Kbyte data cache and clock
doubling
•
80960JT — 3.3 V (5 V Tolerant), 16 Kbyte instruction cache, 4 Kbyte data cache and clock
tripling
2.0
80960Jx Overview
The 80960Jx offers high performance to cost-sensitive 32-bit embedded applications. The 80960Jx
is object code compatible with the 80960 Core Architecture and is capable of sustained execution
at the rate of one instruction per clock. This processor’s features include generous instruction
cache, data cache and data RAM. It also boasts a fast interrupt mechanism and dual-programmable
timer units.
The 80960Jx’s clock multiplication operates the processor core at two or three times the bus clock
rate to improve execution performance without increasing the complexity of board designs.
Memory subsystems for cost-sensitive embedded applications often impose substantial wait state
penalties. The 80960Jx integrates considerable storage resources on-chip to decouple CPU
execution from the external bus.
Advance Information Datasheet
7
INTEL [ INTEL CORPORATION ]
