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80960MC 参数 Datasheet PDF下载

80960MC图片预览
型号: 80960MC
PDF下载: 下载PDF文件 查看货源
内容描述: 具有集成浮点单元和内存管理单元采用嵌入式32位微处理器 [EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT]
分类和应用: 内存管理单元微处理器
文件页数/大小: 39 页 / 401 K
品牌: INTEL [ INTEL CORPORATION ]
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80960MC
FIGURES
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TABLES
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80960MC Instruction Set ........................................................................................................... 3
Memory Addressing Modes ....................................................................................................... 4
Sample Floating-Point Execution Times (µs) at 25 MHz ........................................................... 7
80960MC Pin Description: L-Bus Signals .................................................................................. 9
80960MC Pin Description: Support Signals ............................................................................. 11
DC Characteristics ................................................................................................................... 17
80960MC AC Characteristics (25 MHz) ...................................................................................20
80960MC PGA Pinout — In Pin Order .....................................................................................26
80960MC PGA Pinout — In Signal Order ................................................................................ 27
80960MC PGA Package Thermal Characteristics ................................................................... 28
80960MC Programming Environment ........................................................................................ 1
Instruction Formats .................................................................................................................... 4
Multiple Register Sets Are Stored On-Chip ............................................................................... 6
Connection Recommendations for Low Current Drive Network .............................................. 13
Connection Recommendations for High Current Drive Network .............................................. 13
Typical Supply Current vs. Case Temperature ........................................................................ 14
Typical Current vs. Frequency (Room Temp) .......................................................................... 14
Typical Current vs. Frequency (Hot Temp) .............................................................................. 15
Worst-Case Voltage vs. Output Current on Open-Drain Pins .................................................. 15
Capacitive Derating Curve ....................................................................................................... 15
Test Load Circuit for Three-State Output Pins ......................................................................... 16
Test Load Circuit for Open-Drain Output Pins ......................................................................... 16
Drive Levels and Timing Relationships for 80960MC Signals ................................................. 18
Timing Relationship of L-Bus Signals ................................................................................ ...... 19
System and Processor Clock Relationship ............................................................................. . 19
Processor Clock Pulse (CLK2) ................................................................................................ 21
RESET Signal Timing .............................................................................................................. 21
HOLD Timing ........................................................................................................................... 22
132-Lead Pin-Grid Array (PGA) Package ................................................................................ 23
80960MC PGA Pinout—View from Bottom (Pins Facing Up) .................................................. 24
80960MC PGA Pinout—View from Top (Pins Facing Down) .................................................. 25
25 MHz Maximum Allowable Ambient Temperature ................................................................ 29
Non-Burst Read and Write Transactions Without Wait States ................................................. 30
Burst Read and Write Transaction Without Wait States .......................................................... 31
Burst Write Transaction with 2, 1, 1, 1 Wait States .................................................................. 32
Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from
Quad Word Boundary (1, 0, 0, 0 Wait States) ......................................................................... 33
Interrupt Acknowledge Transaction ......................................................................................... 34
Bus Exchange Transaction (PBM = Primary Bus Master, SBM = Secondary Bus Master) ..... 35
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