80960MC
1.1.16 Inter-Agent Communications (IAC)
System manufacturers can use the 80960MC’s self-
test feature during incoming parts inspection. No
special diagnostic programs need to be written. The
test is both thorough and fast. The self-test capability
helps ensure that defective parts are discovered
before systems are shipped and, once in the field,
the self-test makes it easier to distinguish between
problems caused by processor failure and problems
resulting from other causes.
To coordinate their actions, processors in a multiple
processor system need a means for communicating
with each other. The 80960MC does this through a
mechanism known as “IACs” — Inter-Agent Commu-
nication messages.
IAC messages cause a variety of actions including
starting and stopping processors, flushing instruction
caches and TLBs, and sending interrupts to other
processors in the system. The upper 16 Mbytes of
the processor’s physical memory space is reserved
for sending and receiving IAC messages.
1.1.18 Compatibility with 80960K-Series
Application programs written for the 80960K-Series
microprocessors can be run on the 80960MC
without modification. The 80960K-Series instruction
set forms the core of the 80960MC’s instructions, so
binary compatibility is assured.
1.1.17 Built-in Testability
Upon reset, the 80960MC automatically conducts an
exhaustive internal test of its major blocks of logic.
Then, before executing its first instruction, it does a
zero check sum on the first eight words in memory to
ensure that the memory image was programmed
correctly. When a problem is discovered at any point
during the self-test, the 80960MC asserts its
FAILURE pin and does not begin program execu-
tion. Self test takes approximately 47,000 cycles to
complete.
1.1.19 CHMOS
The 80960MC is fabricated using Intel’s CHMOS IV
(Complementary High Speed Metal Oxide Semicon-
ductor) process. The 80960MC is currently available
at 25 MHz.
Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 1 of 3)
NAME
CLK2
TYPE
DESCRIPTION
I
SYSTEM CLOCK provides the fundamental timing for 80960MC systems. It is
divided by two inside the 80960MC to generate the internal processor clock. Refer
to Figure 16, Processor Clock Pulse (CLK2) (pg. 21)
LAD31:0
I/O
T.S.
LOCAL ADDRESS / DATA BUS carries 32-bit physical addresses and data to and
from memory. During an address (Ta) cycle, bits 2-31 contain a physical word
address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, bits 0-31
contain read or write data. These pins float to a high impedance state when not
active.
Bits 0-1 comprise SIZE during a Ta cycle. SIZE specifies burst transfer size in
words.
LAD1
LAD0
0
0
1
1
0
1
0
1
1 Word
2 Words
3 Words
4 Words
ALE
O
T.S.
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
asserted during a Ta cycle and deasserted before the beginning of the Td state. It is
active LOW and floats to a high impedance state during a hold cycle (Th).
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
PRELIMINARY
9
INTEL [ INTEL ]
