80960HA/HD/HT
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80960Hx Block Diagram .......................................................................................1
80960Hx 168-Pin PGA Pinout — View from Top (Pins Facing Down) ...............12
80960Hx 168-Pin PGA Pinout — View from Bottom (Pins Facing Up) ...............13
80960Hx 208-Pin PQ4 Pinout .............................................................................18
Measuring 80960Hx PGA Case Temperature ....................................................23
80960Hx Device Identification Register ..............................................................26
VCC5 Current-Limiting Resistor ..........................................................................30
AC Test Load ......................................................................................................37
CLKIN Waveform ................................................................................................38
Output Delay Waveform......................................................................................38
Output Delay Waveform......................................................................................38
Output Float Waveform .......................................................................................39
Input Setup and Hold Waveform .........................................................................39
NMI, XINT7:0 Input Setup and Hold Waveform ..................................................39
Hold Acknowledge Timings .................................................................................40
Bus Backoff (BOFF) Timings ..............................................................................40
TCK Waveform....................................................................................................41
Input Setup and Hold Waveforms for T
BSIS1
and T
BSIH1
....................................41
Output Delay and Output Float for T
BSOV1
and T
BSOF1
......................................42
Output Delay and Output Float Waveform for T
BSOV2
and T
BSOF2
....................42
Input Setup and Hold Waveform for T
BSIS2
and T
BSIH2
......................................42
Rise and Fall Time Derating at 85°C and Minimum V
CC
....................................43
I
CC
Active (Power Supply) vs. Frequency ...........................................................43
I
CC
Active (Thermal) vs. Frequency ....................................................................44
Output Delay or Hold vs. Load Capacitance .......................................................44
Output Delay vs. Temperature ............................................................................45
Output Hold Times vs. Temperature ...................................................................45
Output Delay vs. V
CC
..........................................................................................45
Cold Reset Waveform .........................................................................................46
Warm Reset Waveform .......................................................................................47
Entering ONCE Mode .........................................................................................48
Non-Burst, Non-Pipelined Requests without Wait States ...................................49
Non-Burst, Non-Pipelined Read Request with Wait States.................................50
Non-Burst, Non-Pipelined Write Request with Wait States .................................51
Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus .................52
Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus ......................53
Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus .................54
Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus ......................55
Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus ......................56
Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus ........................57
Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus .................58
Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus ......................59
Burst, Pipelined Read Request without Wait States, 32-Bit Bus.........................60
Burst, Pipelined Read Request with Wait States, 32-Bit Bus..............................61
Burst, Pipelined Read Request with Wait States, 8-Bit Bus................................62
Burst, Pipelined Read Request with Wait States, 16-Bit Bus..............................63
Using External READY........................................................................................64
Terminating a Burst with BTERM........................................................................65
BREQ and BSTALL Operation ............................................................................66
iv
Advance Information
Datasheet
INTEL [ INTEL CORPORATION ]
