80960CA-33, -25, -16
3.0
3.1
PACKAGE INFORMATION
Package Introduction
I
Table 2. Pin Description Nomenclature
Symbol
Input only pin
Output only pin
Pin can be either an input or output
Pins “must be” connected as described
Synchronous. Inputs must meet setup
and hold times relative to PCLK2:1 for
proper operation. All outputs are
synchronous to PCLK2:1.
S(E)
Edge sensitive input
S(L)
Level sensitive input
Asynchronous. Inputs may be
asynchronous to PCLK2:1.
A(E)
Edge sensitive input
A(L)
Level sensitive input
While the processor’s bus is in the
Hold Acknowledge or Bus Backoff state,
the pin:
H(1)
is driven to V
CC
H(0)
is driven to V
SS
H(Z)
floats
H(Q)
continues to be a valid input
While the processor’s RESET pin is low,
the pin:
R(1)
is driven to V
CC
R(0)
is driven to V
SS
R(Z)
floats
R(Q)
continues to be a valid output
O
I/O
–
S(...)
Description
This section describes the pins, pinouts and thermal
characteristics for the 80960CA in the 168-pin
Ceramic Pin Grid Array (PGA) package and the 196-
pin Plastic Quad Flat Package (PQFP). For complete
package specifications and information, see the
Packaging
Handbook (Order No. 240800).
3.2
Pin Descriptions
A(...)
The 80960CA pins are described in this section.
Table 2 presents the legend for interpreting the pin
descriptions in the following tables. Pins associated
with the 32-bit demultiplexed processor bus are
described in Table 3. Pins associated with basic
processor configuration and control are described in
Table 4. Pins associated with the 80960CA DMA
Controller and Interrupt Unit are described in Table
5.
All pins float while the processor is in the ONCE
mode.
H(...)
R(...)
4
INTEL [ INTEL CORPORATION ]
