Introduction
• Enhanced Intel SpeedStep technology — Enhanced Intel SpeedStep technology is the next
generation implementation of the Geyserville technology which extends power management
capabilities of servers.
• FC-mPGA4 — The processor is available in a Flip-Chip Micro Pin Grid Array 4 package,
consisting of a processor core mounted on a pinned substrate with an integrated heat spreader
(IHS). This packaging technology employs a 1.27 mm [0.05 in] pitch for the substrate pins.
• Front Side Bus (FSB) — The electrical interface that connects the processor to the chipset.
Also referred to as the processor system bus or the system bus. All memory and I/O
transactions as well as interrupt messages pass between the processor and chipset over the
FSB.
• Functional Operation — Refers to the normal operating conditions in which all processor
specifications, including DC, AC, system bus, signal quality, mechanical, and thermal, are
satisfied.
• Integrated Heat Spreader (IHS) — A component of the processor package used to enhance
the thermal performance of the package. Component thermal solutions interface with the
processor at the IHS surface.
• mPGA604 — The processor mates with the system board through this surface mount,
604-pin, zero insertion force (ZIF) socket.
• OEM — Original Equipment Manufacturer.
• Processor core — The processor’s execution engine. All AC timing and signal integrity
specifications are to the pads of the processor core.
• Processor Information ROM (PIROM) — A memory device located on the processor and
accessible via the System Management Bus (SMBus) which contains information regarding
the processor’s features. This device is shared with the Scratch EEPROM, is programmed
during manufacturing, and is write-protected.
• Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory) — A
memory device located on the processor and addressable via the SMBus which can be used by
the OEM to store information useful for system management.
• SMBus — System Management Bus. A two-wire interface through which simple system and
power management related devices can communicate with the rest of the system. It is based on
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the principals of the operation of the I C* two-wire serial bus from Phillips Semiconductor.
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Note: I C is a two-wire communications bus/protocol developed by Philips. SMBus is a
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subset of the I C bus/protocol and was developed by Intel. Implementations of the I C
bus/protocol or the SMBus bus/protocol may require licenses from various entities,
including Philips Electronics N.V. and North American Philips Corporation.
• Storage Conditions — Refers to a non-operational state. The processor may be installed in a
platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air.
Under these conditions, processor pins should not be connected to any supply voltages, have
any I/Os biased, or receive any clocks.
• Symmetric Agent - A symmetric agent is a processor which shares the same I/O subsystem
and memory array, and runs the same operating system as another processor in a system.
Systems using symmetric agents are known as Symmetric MultiProcessing (SMP) systems.
®
The 64-bit Intel Xeon™ processor MP with up to 8MB L3 cache should only be used in SMP
systems which have two or fewer symmetric agents per front side bus.
64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet
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INTEL [ INTEL ]
