Pentium® III Processor for the SC242 at 450 MHz to 733 MHz
2.0
Electrical Specifications
2.1
Processor System Bus and V
REF
Most Intel® Pentium® III processor signals use a variation of the low voltage Gunning Transceiver
Logic (GTL) signaling technology.
The Pentium Pro processor system bus specification is similar to the GTL specification, but was
enhanced to provide larger noise margins and reduced ringing. The improvements are
accomplished by increasing the termination voltage level and controlling the edge rates. This
specification is different from the GTL specification, and is referred to as GTL+. For more
information on GTL+ specifications, see the GTL+ buffer specification in the Pentium® II
Processor Developer’s Manual (Order Number 243502).
The Pentium III processor varies from the Pentium Pro processor in its output buffer
implementation. The buffers that drive the system bus signals on the Pentium III processor are
actively driven to VCCCORE for one clock cycle after the low to high transition to improve rise
times. These signals should still be considered open-drain and require termination to a supply that
provides the high signal level. Because this specification is different from the GTL+ specification,
it is referred to as AGTL+ in this and other documentation. AGTL+ logic and GTL+ logic are
compatible with each other and may both be used on the same system bus. For more information on
AGTL+ routing, see AP-906, 100 MHz AGTL+ Layout Guidelines for the Pentium III® Processor
and Intel® 440BX AGPset (Order Number 245086) or the appropriate platform design guide.
AGTL+ inputs use differential receivers which require a reference signal (VREF). VREF is used by the
receivers to determine if a signal is a logical 0 or a logical 1, and is generated on the S.E.C.C. and
S.E.C.C.2 packages for the processor core. Local VREF copies should be generated on the baseboard
for all other devices on the AGTL+ system bus. Termination (usually a resistor at each end of the
signal trace) is used to pull the bus up to the high voltage level and to control reflections on the
transmission line. The processor contains termination resistors that provide termination for one end
of the Pentium III processor system bus. These specifications assume another resistor at the end of
each signal trace to ensure adequate signal quality for the AGTL+ signals; see Table 11 for the bus
termination voltage specifications for AGTL+. Refer to the Pentium® II Processor Developer’s
Manual (Order Number 243502) for the GTL+ bus specification. Solutions exist for single-ended
termination as well, though this implementation changes system design. Figure 2 is a schematic
representation of AGTL+ bus topology with Pentium III processors.
The AGTL+ bus depends on incident wave switching. Therefore timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
Pentium III processor system bus including trace lengths is highly recommended when designing a
system with a heavily loaded AGTL+ bus, especially for systems using a single set of termination
resistors (i.e., those on the processor substrate). Such designs will not match the solution space
allowed for by installation of termination resistors on the baseboard. See Intel’s Developer’s
Website (http://developer.intel.com) to download the Pentium® III Processor I/O Buffer Models,
Viewlogic* XTK* model format (formerly known as QUAD format).
Datasheet
13
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