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8031AH_95 参数 Datasheet PDF下载

8031AH_95图片预览
型号: 8031AH_95
PDF下载: 下载PDF文件 查看货源
内容描述: NMOS单芯片8位微控制器 [NMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS]
分类和应用: 微控制器
文件页数/大小: 11 页 / 168 K
品牌: INTEL [ INTEL CORPORATION ]
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AUTOMOTIVE MICROCONTROLLER MCS 51
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature
Under Bias
Storage Temperature
Voltage on EA VPP Pin to V
SS
Voltage on Any Other Pin to V
SS
b
40 C to
a
110 C
b
65 C to
a
150 C
b
0 5V to
a
21 5V
b
0 5V to
a
7V
NOTICE This is a production data sheet The specifi-
cations are subject to change without notice
WARNING Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage
These are stress ratings only Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability
Power Dissipation
1 5W
Based on package heat transfer limitations not de-
vice power consumption
Maximum Case Temperature
a
125 C
Under Bias
Typical Thermal Resistance Junction to Ambient (i
JA
)
Package
Plastic DIP
i
JA
75 C W
DC CHARACTERISTICS
Symbol
V
IL
V
IH
V
IH1
V
OL
V
OL1
V
OH
V
OH1
I
IL
Input Low Voltage
T
A
e b
40 C to
a
110 C V
CC
e
5V
g
10% V
SS
e
0V
Min
b
0 5
Parameter
Max
07
V
CC
a
0 5
V
CC
a
0 5
0 45
0 45
Units
V
V
V
V
V
V
V
Test Conditions
Input High Voltage (Except XTAL2 RST)
Input High Voltage to XTAL2 RST
Output Low Voltage (Ports 1 2 3)
Output Low Voltage (Port 0 ALE PSEN)
Output High Voltage (Ports 1 2 3 ALE PSEN)
Output High Voltage (Port 0 in
External Bus Mode)
Logical 0 Input Current (Ports 1 2 3
RST) 8032AH 8052AH
All Others
Logical 0 Input Current (XTAL2)
Input Leakage Current (Port 0)
Input Current to RST to Activate Reset
Power Supply Current
8031 8051
8031AH 8051AH
8032AH 8052AH
Pin Capacitance
21
26
XTAL1
e
V
SS
I
OL
e
1 6 mA
I
OL
e
3 2 mA
I
OH
e b
80
mA
I
OH
e b
400
mA
24
24
b
800
b
500
b
4 0
g
10
mA
mA
mA
mA
mA
mA
mA
mA
pF
V
IN
e
0 45V
V
IN
e
0 45V
V
IN
e
0 45V
0 45
s
V
IN
s
V
CC
V
IN
k
(V
CC
b
1 5V)
I
IL2
I
LI
I
IH1
I
CC
500
175
135
175
10
All Outputs
Disconnected
Test freq
e
1 MHz
C
IO
NOTE
Capacitive loading on Ports 0 and 2 may cause noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3
The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-to-0
transitions during bus operations In the worst cases (capacitive loading
l
100 pF) the noise pulse on the ALE line may
exceed 0 8V In such cases it may be desirable to qualify ALE with a Schmitt Trigger or use an address latch with a Schmitt
Trigger STROBE input
6