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e
Master Interface Timing Responses (Continued)
a
e
CC
g
5V 10%) (Continued)
A.C. CHARACTERISTICS (T
0 C to 70 C, V
§
§
A
8 MHz
Min
10 MHz
Test
Symbol
Parameter
Units
Conditions
Max
Min
0
Max
T
Address Float to RD Active
RD Active Delay
0
ns
ns
ns
ns
AZRL
CLRL
CLRH
RHAV
T
T
T
10
10
70
55
10
10
56
44
RD Inactive Delay
b
b
40
RD Inactive to Address
Active
T
40
T
CLCL
CLCL
T
T
T
T
T
T
T
HLDA Valid Delay
RD Width
5
50
5
40
ns
ns
ns
ns
ns
ns
ns
CLHAV
RLRH
WLWH
AVLL
b
b
2T
2T
50
40
25
2T
2T
46
34
19
CLCL
CLCL
CLCL
b
b
WR Width
CLCL
b
b
CLCH
Address Valid to ALE Low
Status Active Delay
Status Inactive Delay
Timer Output Delay
T
T
CLCH
10
10
55
65
60
10
10
45
50
48
CHSV
CLSH
100 pF max
@
CLTMV
8 & 10 MHz
T
T
T
T
T
Reset Delay
60
35
48
28
ns
ns
ns
ns
ns
CLRO
CHQSV
CHDX
AVCH
CLLV
Queue Status Delay
Status Hold Time
10
10
5
10
10
5
Address Valid to Clock High
LOCK Valid/Invalid Delay
65
66
60
45
Chip-Select Timing Responses
T
T
Chip-Select Active Delay
ns
ns
CLCSV
CXCSX
Chip-Select Hold from
Command Inactive
35
5
35
5
T
Chip-Select Inactive Delay
35
32
ns
CHCSX
CLKIN Requirements
T
T
T
T
T
CLKIN Period
62.5
250
10
50
250
10
ns
ns
ns
ns
ns
CKIN
CLKIN Fall Time
CLKIN Rise Time
CLKIN Low Time
CLKIN High Time
3.5 to 1.0V
1.0 to 3.5V
1.5V
CKHL
CKLH
CLCK
CHCK
10
10
25
25
20
20
1.5V
CLKOUT Timing (200 pF load)
T
T
T
T
T
T
CLKIN to CLKOUT Skew
CLKOUT Period
50
25
ns
ns
ns
ns
ns
ns
CICO
125
500
100
500
CLCL
b
b
CLKOUT Low Time
CLKOUT High Time
CLKOUT Rise Time
CLKOUT Fall Time
(/2 T
(/2 T
7.5
(/2 T
(/2 T
6.0
6.0
1.5V
CLCH
CLCL
CLCL
CLCL
CLCL
b
b
7.5
1.5V
CHCL
15
15
12
12
1.0 to 3.5V
3.5 to 1.0V
CH1CH2
CL2CL1
17
17
INTEL [ INTEL ]
