80186/80188
e
a
e
5V 10%)
CC
g
A.C. CHARACTERISTICS (T
0 C to 70 C, V
§
§
A
Timing Requirements All Timings Measured At 1.5V Unless Otherwise Noted.
8 MHz
Min
10 MHz
Min
Test
Symbol
Parameter
Units
Conditions
Max
Max
T
Data in Setup (A/D)
Data in Hold (A/D)
20
10
20
15
8
ns
ns
ns
DVCL
T
T
CLDX
Asynchronous Ready
(ARDY) Active Setup
(1)
Time
15
ARYHCH
T
T
T
ARDY Inactive Setup Time
ARDY Hold Time
35
15
15
25
15
15
ns
ns
ns
ARYLCL
CLARX
Asynchronous Ready
Inactive Hold Time
ARYCHL
T
T
Synchronous Ready (SRDY)
(2)
Transition Setup Time
20
15
20
15
ns
ns
SRYCL
CLSRY
SRDY Transition Hold
(2)
Time
(1)
T
T
HOLD Setup
25
25
20
25
ns
ns
HVCL
INTR, NMI, TEST, TIM IN,
(1)
Setup
INVCH
(1)
T
DRQ0, DRQ1, Setup
25
20
ns
INVCL
Master Interface Timing Responses
e
L
T
CLAV
T
CLAX
T
CLAZ
T
CHCZ
T
CHCV
Address Valid Delay
Address Hold
5
55
5
44
ns
ns
ns
ns
ns
C
20 pF–200 pF
all Outputs
(Except T
10
10
@
)
CLTMV
8 MHz and 10 MHz
Address Float Delay
Command Lines Float Delay
T
35
45
55
T
30
40
45
CLAX
CLAX
Command Lines Valid Delay
(after Float)
b
b
b
b
T
T
T
T
ALE Width
T
35
T
30
ns
ns
ns
ns
LHLL
CHLH
CHLL
LLAX
CLCL
CLCL
ALE Active Delay
ALE Inactive Delay
35
35
30
30
Address Hold from ALE
Inactive
T
CHCL
25
T
T
20
CHCL
T
T
T
T
T
T
T
Data Valid Delay
10
10
44
10
10
40
ns
ns
ns
ns
ns
ns
ns
CLDV
Data Hold Time
CLDOX
WHDX
CVCTV
CHCTV
CVCTX
CVDEX
b
b
34
Data Hold after WR
Control Active Delay 1
Control Active Delay 2
Control Inactive Delay
T
40
CLCL
5
CLCL
5
50
55
55
70
40
44
44
56
10
5
10
5
DEN Inactive Delay
(Non-Write Cycle)
10
10
1. To guarantee recognition at next clock.
2. To guarantee proper operation.
16
16
INTEL [ INTEL ]
