FBD Channel Interface
2.3.4
Address Mapping of DDR Commands to DRAMs
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DDR2 x4 Config
256Mb (64Mbx4) Row
1
0
1
0
1
0
1
X
1
X
1
X
1
X
X
RS
X
X
X
X
X
X
B1 B0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
B1 B0 A11 AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
B1 B0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
B1 B0 A11 AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1KB page
Col
r/w RS
X
r/w RS
X
512Mb (128Mbx4) Row
RS A13
1KB page
1Gb (256Mbx4)
1KB page
Col
Row
Col
X
X
X
RS A13 B2 B1 B0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
r/w RS B2 B1 B0 A11 AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A14 RS A13 B2 B1 B0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
r/w RS B2 B1 B0 A11 AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
X
X
2Gb (512Mbx4)
1KB page
Row
Col
0
1
X
X
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DDR2 x8 Config
256Mb (32Mbx8) Row
1KB page Col
512Mb (64Mbx8) Row
1
0
1
0
1
0
1
X
1
X
1
X
1
X
X
RS
X
X
X
X
X
X
B1 B0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
B1 B0 AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
B1 B0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
B1 B0 AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
r/w RS
X
r/w RS
X
X
RS A13
1KB page
1Gb (128Mbx8)
1KB page
Col
Row
Col
X
X
X
X
RS A13 B2 B1 B0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
r/w RS B2 B1 B0 AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A14 RS A13 B2 B1 B0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
X
X
X
2Gb (256Mbx8)
Row
2.3.5
FBD L0s State
The L0s state is not supported in the AMB.
2.4
Reliability, Availability, and Serviceability
Refer to Chapter 5, “Reliability, Availability and Serviceability” in the FB DIMM
Architecture and Protocol Specification [1] for FBD RAS requirements.
2.4.1
Channel Error Detection and Logging
See for details on the error handling.
2.5
Channel Configuration
2.5.1
Re-sync and Resample Modes
A separate control is available for both the NB and SB FBD links to select between lower
latency re-sample and lower jitter re-sync modes for repeating received data. Selection
between these two modes is a function of platform design and configuration and should
be set by BIOS prior to link initialization
The FBDSBCFGNXT.SBRESYNCEN and FBDNBCFGNXT.NBRESYNCEN bits make
this selection.
Descriptions of these two modes follows.
2.5.1.1
Accumulated Tracking Effects (Re-Sample Option)
Each AMB acts as a repeater for the FBD channel. Since the data driven from each
DIMM to the next DIMM may experience random or periodic phase shifts, the effect of
these phase shifts must be accommodated in the design. Consider a system with three
DIMMs daisy-chained together. A phase shift generated in the first DIMM will be seen by
the second DIMM but will not be immediately propagated to the third DIMM. Unlike an
analog buffer, the phase shift is not automatically driven to subsequent DIMMs since
Intel® 6400/6402 Advanced Memory Buffer Datasheet
19
INTEL [ INTEL ]
