Registers
14.3.1.14 FBDLOCKTO: FBD Bit Lock Time Out Register
This register contains the bit lock time out value. This value is used by the to figure out
when it should stop waiting for lanes to bit lock and make forward progress. The
register also contains the width that the host is going to be starting with on the NB
side. This will be used to mask off lanes for initial bit lock decision
Device:
NodeID
Function: 1
Offset:
68h
Bit
Attr
Default
Description
BLTOCNT: Bit Lock Time Out Counter
15:2
RWST
0594h
default: 1428 frames
1:0
RWST
0h
NBLINKCFG: Northbound Link Config
00 = 14 lane
01 = 13 lane
10 = 12 lane
11 = reserved
14.3.1.15 FBDHAC: FBD Hot Add Control
This register contains control to aid in hot add functionality.
Device:
NodeID
Function: 1
Offset:
Bit
6Ch
Attr
Default
Description
7:2
1
RV
RO
0
0
Reserved
NB_DATA_ALL_ONES_FLAG:
•
•
1 = Receiving ones on sufficient NB lanes to support init
0 = Not receiving calibrate handshake on NB Rx
0
RW
0
DRIVE_ONES_SB:
•
•
1 = Enable SB Tx Outputs and drive one’s
0 = Normal operation
14.3.1.16 FBDLS: FBD Link Status
This register reports AMB FBD link status.
Device:
NodeID
Function: 1
Offset:
Bit
6Eh
Attr
Default
Description
7:3
2
RV
RO
0h
0
Reserved
NLQS: Northbound Lane Electrical Status
‘1’ = Northbound lanes are quiesced
‘0’ = Northbound lanes are active
1
0
RO
RO
0
0
SLQS: Southbound Lane Electrical Status
‘1’ = Southbound lanes are quiesced
‘0’ = Southbound lanes are active
LNKRDY: Link Ready
‘1’ = FBD link is ready to accept requests and deliver responses
‘0’ = FBD link is not ready
178
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
