7–4
Chapter 7: User Flash Memory in MAX V Devices
UFM Functional Description
Table 7–4. UFM Interface Signals (Part 2 of 2)
Port Name
Port Type
Description
Signal that initiates a program sequence. On the rising edge, the data in the data register is
written to the address pointed to by the address register. The BUSYsignal asserts until the
program sequence is completed.
PROGRAM
Input
Signal that initiates an erase sequence. On a rising edge, the memory sector indicated by
the MSB of the address register is erased. The BUSYsignal asserts until the erase sequence
is completed.
ERASE
Input
Input
This signal turns on the internal oscillator in the UFM block. It is required when the OSC
output is used, but optional otherwise. If OSC_ENAis driven high, the internal oscillator is
enabled and the OSCoutput will toggle. If OSC_ENAis driven low, the internal oscillator is
disabled and the OSCoutput drives constant high.
OSC_ENA
Serial output of the data register. Each time the DRCLKsignal is applied, a new value is
available. The DRDoutdata depends on the DRSHFTsignal. When the DRSHFTsignal is high,
DRDoutcontains the new value that is shifted into the MSB of the data register. If DRSHFTis
low, DRDoutcontains the MSB of the memory location read into the data register.
DRDout
Output
Signal that indicates when the memory is BUSYperforming a PROGRAMor ERASE
instruction. When it is high, the address and data register should not be clocked. The new
PROGRAMor ERASEinstruction is not executed until the BUSYsignal is deasserted.
BUSY
OSC
Output
Output
Output of the internal oscillator. It can be used to generate a clock to control user logic with
the UFM. It requires an OSC_ENAinput to produce an output.
This output signal is optional and only needed if the real-time ISP feature is used. The signal
is asserted high during real-time ISP and stays in the RUN_STATEfor 500 ms before
initiating real-time ISP to allow for the final read/erase/write operation. No read, write,
erase, or address and data shift operations are allowed to be issued after the RTP_BUSY
signal goes high. The data and address registers do not retain the contents of the last read
or write operation for the UFM block during real-time ISP.
RTP_BUSY
Output
f For more information about the interaction between the UFM block and the logic
array of MAX V devices, refer to the MAX V Device Architecture chapter.
MAX V Device Handbook
January 2011 Altera Corporation
INTEL [ INTEL ]
