6–4
Chapter 6: JTAG and In-System Programmability in MAX V Devices
IEEE Std. 1149.1 Boundary-Scan Support
f For more information about JTAG BST, refer to the JTAG Boundary-Scan Testing for
MAX V Devices chapter.
JTAG Block
If you issue either the USER0or USER1instruction to the JTAG test access port (TAP)
controller, the MAX V JTAG block feature allows you to access the JTAG TAP
controller and state signals. The USER0and USER1instructions bring the JTAG
boundary-scan chain (TDI) through the user logic instead of the boundary-scan cells
(BSCs) of MAX V devices. Each USERinstruction allows for one unique user-defined
JTAG chain into the logic array.
Parallel Flash Loader
MAX V devices have the ability to interface JTAG to non-JTAG devices and are
suitable to use with the general flash memory devices that require programming
during the in-circuit test. You can use the flash memory devices for FPGA
configuration or be part of the system memory. In many cases, you can use the
MAX V device as a bridge device that controls configuration between FPGA and flash
devices. Unlike ISP-capable CPLDs, bulk flash devices do not have JTAG TAP pins or
connections. For small flash devices, it is common to use the serial JTAG scan chain of
a connected device to program the non-JTAG flash device but this is slow, inefficient,
and impractical for large parallel flash devices. Using the MAX V JTAG block as a
parallel flash loader (PFL) with the Quartus II software to program and verify flash
contents provides a fast and cost-effective means of in-circuit programming during
testing.
f For more information about PFL, refer to the Parallel Flash Loader Megafunction User
Guide.
MAX V Device Handbook
May 2011 Altera Corporation
INTEL [ INTEL ]
