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5M80ZE64I5N 参数 Datasheet PDF下载

5M80ZE64I5N图片预览
型号: 5M80ZE64I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, 64-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用:
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
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3–28  
Chapter 3: DC and Switching Characteristics for MAX V Devices  
Timing Model and Specifications  
Table 3–40 lists the emulated RSDS output timing specifications for MAX V devices.  
Table 3–40. Emulated RSDS Output Timing Specifications for MAX V Devices  
5M40Z/ 5M80Z/ 5M160Z/  
5M240Z/ 5M570Z/5M1270Z/  
5M2210Z  
Parameter  
Mode  
Unit  
C4, C5, I5  
Min  
Max  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
55  
10  
9  
8  
7  
6  
5  
4  
3  
2  
1  
45  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
%
Data rate (1)  
tDUTY  
Total jitter (2)  
tRISE  
0.2  
UI  
450  
450  
ps  
tFALL  
ps  
Notes to Table 3–40:  
(1) For the input clock pin to achieve 200 Mbps, use I/O standard with VCCIO of 1.8 V and above.  
(2) This specification is based on external clean clock source.  
MAX V Device Handbook  
May 2011 Altera Corporation  
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