Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
8–13
I/O Voltage Support in the JTAG Chain
USERCODE Instruction Mode
Use USERCODEinstruction mode to examine the user electronic signature (UES) within
the devices along an IEEE Std. 1149.1 chain. When you select this instruction, the
device identification register is connected between the TDIand TDOports. The user-
defined UES shifts into the device ID register in parallel from the 32-bit USERCODE
register. The UES then shifts out through the device ID register. The USERCODE
information is only available after the device is successfully configured.
Non-volatile USERCODEdata is written to the configuration flash memory (CFM) block
and then written to the SRAM at power up. The USERCODEinstruction reads the data
values from the SRAM. When you use real-time ISP to update the CFM block and
write new USERCODEdata, executing the USERCODEinstruction returns the USERCODEof
the current running design (stored in the SRAM), not the new USERCODEdata. The
USERCODEof the new design (stored in the CFM) can only be read back correctly if a
power cycle or forced SRAM download has transpired after the real-time ISP update.
In the Quartus® II software, there is an Auto Usercode feature where you can choose
to use the checksum value of a programming file as the JTAG user code. If selected,
the checksum is automatically loaded to the USERCODEregister.
To enable the Auto Usercode feature, follow these steps:
1. On the Assignments menu, click Device.
2. In the Device dialog box, click Device and Pin Options and click the General tab.
3. Turn on Auto Usercode.
CLAMP Instruction Mode
Use CLAMPinstruction mode to allow the state of the signals driven from the pins to be
determined from the boundary-scan register while the bypass register is selected as
the serial path between the TDIand Tmv51008.fmDOports. Data held in the boundary-
scan register completely defines the state of all signals driven from the output pins.
However, CLAMPinstruction mode will not override the I/O weak pull-up resistor or
the I/O bus hold if you have any of them selected.
HIGHZ Instruction Mode
Use HIGHZinstruction mode to set all of the user I/O pins to an inactive drive state.
These pins are tri-stated until you execute a new JTAG instruction. When you select
this instruction, the bypass register is connected between the TDIand TDOports. HIGHZ
instruction mode will not override the I/O weak pull-up resistor or I/O bus hold if
you have any of them selected.
I/O Voltage Support in the JTAG Chain
There can be several different Altera or non-Altera devices in a JTAG chain. However,
you must pay attention to whether or not the chain contains devices with different
VCCIO levels. The TDOpin of a device drives out at the voltage level according to the
VCCIO of the device. For MAX V devices, the TDOpin drives out at the voltage level
according to the VCCIO of I/O Bank 1. Although the devices may have different VCCIO
December 2010 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
