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5M80ZE64I5N 参数 Datasheet PDF下载

5M80ZE64I5N图片预览
型号: 5M80ZE64I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, 64-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用:
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
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Chapter 7: User Flash Memory in MAX V Devices  
7–43  
Simulation Parameters  
Padding Data into Memory Map  
The ALTUFM_I2C megafunction uses the upper 8 bits of the UFM 16-bit word;  
therefore, the 8 least significant bits should be padded with 1s, as shown in  
Figure 7–41.  
Figure 7–41. Padding Data into Memory Map  
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
8-bit valid data to be placed  
in the upper byte  
Pad the lower byte with eight '1's  
Simulation Parameters  
In the ALTUFM megafunction, you have an option to simulate the OSCoutput port at  
the maximum or the minimum frequency during the design simulation. The  
frequency chosen is only used as the timing parameter for the Quartus II simulator  
and does not affect the real MAX V device OSCoutput frequency.  
Document Revision History  
Table 7–17 lists the revision history for this chapter.  
Table 7–17. Document Revision History  
Date  
Version  
1.1  
Changes  
January 2011  
December 2010  
Updated “Oscillator” section.  
Initial release.  
1.0  
January 2011 Altera Corporation  
MAX V Device Handbook  
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