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5M80ZE64I5N 参数 Datasheet PDF下载

5M80ZE64I5N图片预览
型号: 5M80ZE64I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, 64-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用:
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
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Chapter 7: User Flash Memory in MAX V Devices  
7–41  
Creating Memory Content File  
Memory Map for 2-Kbit Memory Initialization  
Figure 7–38 shows the memory map initialization for the ALTUFM_I2C megafunction  
of 2 Kbits of memory. The ALTUFM_I2C megafunction byte address location of 00hto  
7Fh is mapped to the UFM block address location of 000hto 07Fh. The ALTUFM_I2C  
megafunction byte address location of 80hto FFhis mapped to the UFM block address  
location of 180hto 1FFh. Altera recommends that you pad the unused address location  
of the UFM block with all 1s.  
Figure 7–38. Memory Map for 2-Kbit Memory Initialization  
MIF or HEX File Contents – to represent  
the actual data and address size for the UFM block  
1FFh  
2-Kbit ALTUFM_I2C Megafunction  
Logical Memory Contents  
Address 80h in logical memory maps to  
address 180h in the MIF/HEX file. FFh in logical  
memory maps to 1FFh in the MIF/HEX file, and all  
data in between follows the order in the  
logical memory  
FFh  
Upper Half – Addresses  
80h to FFh  
180h  
17Fh  
This section of the UFM is unused –  
the MIF/HEX file contents should be set to  
all '1' for addresses 080h to 17Fh  
80h  
7Fh  
080h  
07Fh  
Lower Half – Addresses  
00h to 7Fh  
Address 00h in logical memory maps to  
address 000h in the MIF/HEX file. Address 7Fh in  
logical memory maps to 07Fh in the MIF/HEX file,  
and all data in between follows the order in the  
logical memory  
00h  
000h  
January 2011 Altera Corporation  
MAX V Device Handbook  
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