Chapter 6: JTAG and In-System Programmability in MAX V Devices
6–5
In-System Programmability
Figure 6–1 shows how you can use the MAX V JTAG block as a PFL.
Figure 6–1. PFL for MAX V Devices
MAX V Device
Flash
Memory Device
Altera FPGA
CONF_DONE
nSTATUS
nCE
DQ[7..0]
A[20..0]
OE
DQ[7..0]
A[20..0]
OE
WE
WE
CE
CE
RY/BY
RY/BY
DATA0
nCONFIG
DCLK
TDO_U
TDI_U
PFL
Configuration
Logic
TDI
TMS
TCK
TMS_U
TCK_U
SHIFT_U
CLKDR_U
(1),(2)
TDO
UPDATE_U
RUNIDLE_U
USER1_U
Notes to Figure 6–1:
(1) This block is implemented in logic elements (LEs).
(2) This function is supported in the Quartus II software.
In-System Programmability
You can program MAX V devices in-system through the industry standard 4-pin
IEEE Std. 1149.1 interface. ISP offers quick and efficient iterations during design
development and debugging cycles. The flash-based SRAM configuration elements
configure the logic, circuitry, and interconnects in the MAX V architecture. Each time
the device is powered up, the configuration data is loaded into the SRAM elements.
The process of loading the SRAM data is called configuration. The on-chip
configuration flash memory (CFM) block stores the configuration data of the SRAM
element. The CFM block stores the configuration pattern of your design in a
reprogrammable flash array. During ISP, the MAX V JTAG and ISP circuitry programs
the design pattern into the non-volatile flash array of the CFM block.
The MAX V JTAG and ISP controller internally generate the high programming
voltages required to program the CFM cells, allowing in-system programming with
any of the recommended operating external voltage supplies. You can configure the
ISP anytime after you have fully powered VCCINT and all VCCIO banks, and the device
has completed the configuration power-up time. By default, during in-system
programming, the I/O pins are tri-stated and weakly pulled-up to VCCIO banks to
eliminate board conflicts. The in-system programming clamp and real-time ISP
feature allow user control of the I/O state or behavior during ISP.
For more information, refer to “In-System Programming Clamp” on page 6–7 and
“Real-Time ISP” on page 6–8.
These devices also offer an ISP_DONEbit that provides safe operation if in-system
programming is interrupted. This ISP_DONE bit, which is the last bit programmed,
prevents all I/O pins from driving until the bit is programmed.
May 2011 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
