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5M570ZM100I5N 参数 Datasheet PDF下载

5M570ZM100I5N图片预览
型号: 5M570ZM100I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 17.7ns, 440-Cell, CMOS, PBGA100, 6 X 6 MM, 0.50 MM PITCH, LEAD FREE, MBGA-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
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5. Using MAX V Devices in Multi-Voltage  
Systems  
December 2010  
MV51005-1.0  
MV51005-1.0  
This chapter describes how to implement Altera® devices in multi-voltage systems  
without damaging the device or the system.  
Technological advancements in deep submicron processes have lowered the supply  
voltage levels of semiconductor devices, creating a design environment where devices  
on a system board may potentially use many different supply voltages such as 5.0, 3.3,  
2.5, 1.8, 1.5, and 1.2 V, which can ultimately lead to voltage conflicts.  
To accommodate interfacing with a variety of devices on system boards, MAX® V  
devices have MultiVolt I/O interfaces that allow devices in a mixed-voltage design  
environment to communicate directly with MAX V devices. The MultiVolt interface  
separates the power supply voltage (VCCINT) from the output voltage (VCCIO),  
allowing MAX V devices to interface with other devices using a different voltage level  
on the same PCB. The 1.8-V input directly powers the core of the MAX V devices.  
f For more information about hot socketing and power-on reset (POR), refer to the Hot  
Socketing and Power-On Reset in MAX V Devices chapter.  
This chapter contains the following sections:  
“I/O Standards” on page 5–1  
“MultiVolt I/O Operation” on page 5–3  
“5.0-V Device Compatibility” on page 5–3  
“Recommended Operating Conditions for 5.0-V Compatibility” on page 5–7  
“Power-Up Sequencing” on page 5–8  
I/O Standards  
The I/O buffer of MAX V devices is programmable and supports a wide range of I/O  
voltage standards. You can program each I/O bank in a MAX V device to comply  
with a different I/O standard. You can configure all I/O banks with the following  
standards:  
3.3-V LVTTL/LVCMOS  
2.5-V LVTTL/LVCMOS  
1.8-V LVTTL/LVCMOS  
1.5-V LVCMOS  
1.2-V LVCMOS  
Emulated LVDS output (LVDS_E_3R)  
Emulated RSDS output (RSDS_E_3R)  
© 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.  
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at  
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but  
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any  
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device  
specifications before relying on any published information and before placing orders for products or services.  
MAX V Device Handbook  
December 2010  
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