4–4
Chapter 4: Hot Socketing and Power-On Reset in MAX V Devices
Hot-Socketing Feature Implementation in MAX V Devices
Figure 4–2 shows a transistor-level cross section of the MAX V device I/O buffers.
This design ensures that the output buffers do not drive when VCCIO is powered
before VCCINT or if the I/O pad voltage is higher than VCCIO. This also applies for
sudden voltage spikes during hot insertion. The VPAD leakage current charges the
3.3-V tolerant circuit capacitance.
Figure 4–2. Transistor-Level I/O Buffers for MAX V Devices
Ensures 3.3-V
Tolerance and
Hot-Socket
VPAD
IOE Signal or the
Larger of VCCIO or VPAD
The Larger of
VCCIO or VPAD
Protection
IOE Signal
VCCIO
p+
n+
p+
n+
n+
n -well
p -well
p -substrate
The CMOS output drivers in the I/O pins intrinsically provide electrostatic discharge
(ESD) protection. There are two cases to consider for ESD voltage strikes—positive
voltage zap and negative voltage zap.
A positive ESD voltage zap occurs when a positive voltage is present on an I/O pin
due to an ESD charge event. This can cause the N+ (Drain)/ P-Substrate junction of
the N-channel drain to break down and the N+ (Drain)/P-Substrate/N+ (Source)
intrinsic bipolar transistor turn on to discharge ESD current from I/O pin to GND.
The dashed line in Figure 4–3 shows the ESD current discharge path during a positive
ESD zap.
Figure 4–3. ESD Protection During Positive Voltage Zap
I/O
Source
D
Gate
PMOS
N+
Drain
Drain
P-Substrate
G
I/O
S
Gate
N+
NMOS
Source
GND
GND
MAX V Device Handbook
December 2010 Altera Corporation
INTEL [ INTEL ]
