6–6
Chapter 6: JTAG and In-System Programmability in MAX V Devices
In-System Programmability
IEEE 1532 Support
The JTAG circuitry and ISP instruction set in MAX V devices are compliant to the
IEEE-1532-2002 programming specification. This provides industry-standard
hardware and software for in-system programming among multiple vendor
programmable logic devices (PLDs) in a JTAG chain.
f For more information about MAX V 1532 Boundary-Scan Description Language
(.bsd) files, refer to the IEEE 1532 BSDL Files page of the Altera website.
Jam Standard Test and Programming Language
You can use the Jam STAPL to program MAX V devices with in-circuit testers, PCs, or
embedded processors. The Jam byte code is also supported for MAX V devices. These
software programming protocols provide a compact embedded solution for
programming MAX V devices.
f For more information, refer to AN 425: Using Command-Line Jam STAPL Solution for
Device Programming.
Programming Sequence
During in-system programming, 1532 instructions, addresses, and data are shifted
into the MAX V device through the TDIinput pin. Data is shifted out through the TDO
output pin and compared with the expected data.
To program a pattern into the device, follow these steps:
1. Enter ISP—The enter ISP stage ensures that the I/O pins transition smoothly from
user mode to ISP mode.
2. Check ID—The silicon ID is checked before any Program or Verify process. The
time required to read this silicon ID is relatively small compared to the overall
programming time.
3. Sector Erase—Erasing the device in-system involves shifting in the instruction to
erase the device and applying an erase pulse or pulses. The erase pulse is
automatically generated internally by waiting in the run, test, or idle state for the
specified erase pulse time of 500 ms for the CFM block and 500 ms for each sector
of the user flash memory (UFM) block.
4. Program—Programming the device in-system involves shifting in the address,
data, and program instruction and generating the program pulse to program the
flash cells. The program pulse is automatically generated internally by waiting in
the run/test/idle state for the specified program pulse time of 75 µs. This process
is repeated for each address in the CFM and UFM blocks.
5. Verify—Verifying a MAX V device in-system involves shifting in addresses,
applying the verify instruction to generate the read pulse, and shifting out the data
for comparison. This process is repeated for each CFM and UFM address.
6. Exit ISP—An exit ISP stage ensures that the I/O pins transition smoothly from ISP
mode to user mode.
MAX V Device Handbook
May 2011 Altera Corporation
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