1–2
Chapter 1: MAX V Device Family Overview
Feature Summary
■
I/Os are fully compliant with the PCI-SIG® PCI Local Bus Specification, revision
2.2 for 3.3-V operation
■
■
Hot-socket compliant
Built-in JTAG BST circuitry compliant with IEEE Std. 1149.1-1990
Table 1–1 lists the MAX V family features.
Table 1–1. MAX V Family Features
Feature
5M40Z
40
5M80Z
80
5M160Z
160
128
8,192
4
5M240Z
240
192
8,192
4
5M570Z
570
440
8,192
4
5M1270Z 5M2210Z
LEs
1,270
980
8,192
4
2,210
1,700
8,192
4
Typical Equivalent Macrocells
User Flash Memory Size (bits)
Global Clocks
32
64
8,192
4
8,192
4
Internal Oscillator
Maximum User I/O pins
tPD1 (ns) (1)
1
1
1
1
1
1
1
54
79
79
114
7.5
159
9.0
271
6.2
271
7.0
7.5
152
2.3
6.5
7.5
152
2.3
6.5
7.5
fCNT (MHz) (2)
152
2.3
152
2.3
152
2.2
304
1.2
304
1.2
t
SU (ns)
tCO (ns)
6.5
6.5
6.7
4.6
4.6
Notes to Table 1–1:
(1) tPD1 represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and combinational logic
implemented in a single LUT and LAB that is adjacent to the output pin.
(2) The maximum global clock frequency, fCNT, is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay will run faster
than this number.
MAX V devices accept 1.8 V on their VCCINTpins. The 1.8-V VCCINT external supply
powers the device core directly. MAX V devices operate internally at 1.8 V. The
supported MultiVolt I/O interface voltage levels (VCCIO) are 1.2 V, 1.5 V, 1.8 V, 2.5 V,
and 3.3 V.
MAX V devices are available in two speed grades: –4 and –5, with –4 being the fastest.
For commercial applications, speed grades –C4 and –C5 are available. For industrial
and automotive applications, speed grade –I5 and –A5 are available, respectively.
These speed grades represent the overall relative performance, not any specific timing
parameter.
f For propagation delay timing numbers within each speed grade and density, refer to
the DC and Switching Characteristics for MAX V Devices chapter.
MAX V devices are available in space-saving FineLine BGA (FBGA), Micro FineLine
BGA (MBGA), plastic enhanced quad flat pack (EQFP), and thin quad flat pack
(TQFP) packages (refer to Table 1–2 and Table 1–3). MAX V devices support vertical
migration within the same package (for example, you can migrate between the
5M570Z, 5M1270Z, and 5M2210Z devices in the 256-pin FineLine BGA package).
Vertical migration means that you can migrate to devices whose dedicated pins and
JTAG pins are the same and power pins are subsets or supersets for a given package
across device densities. The largest density in any package has the highest number of
power pins; you must lay out for the largest planned density in a package to provide
MAX V Device Handbook
May 2011 Altera Corporation
INTEL [ INTEL ]
