Chapter 2: MAX V Architecture
2–29
I/O Structure
Figure 2–21 shows how a column I/O block connects to the logic array.
Figure 2–21. Column I/O Block Connection to the Interconnect (Note 1)
Column I/O
Block Contains
Up To 4 IOEs
Column I/O Block
data_in
[3..0]
data_out
[3..0]
OE
[3..0]
fast_out
[3..0]
4
4
4
4
I/O Block
Local Interconnect
Fast I/O
Interconnect
Path
LAB Column
Clock [3..0]
R4 Interconnects
LAB
LAB
LAB
LAB Local
Interconnect
LAB Local
Interconnect
LAB Local
Interconnect
C4 Interconnects
C4 Interconnects
Note to Figure 2–21:
(1) Each of the four IOEs in the column I/O block can have one data_outor fast_outoutput, one OEoutput, and
one data_ininput.
I/O Standards and Banks
Table 2–4 lists the I/O standards supported by MAX V devices.
Table 2–4. MAX V I/O Standards (Part 1 of 2)
Output Supply Voltage (VCCIO
)
I/O Standard
Type
(V)
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
3.3
2.5
1.8
1.5
1.2
1.2-V LVCMOS
December 2010 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
