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5M160ZE64C4N 参数 Datasheet PDF下载

5M160ZE64C4N图片预览
型号: 5M160ZE64C4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 7.9ns, 128-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 3966 K
品牌: INTEL [ INTEL ]
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2–10  
Chapter 2: MAX V Architecture  
Logic Elements  
Normal Mode  
The normal mode is suitable for general logic applications and combinational  
functions. In normal mode, four data inputs from the LAB local interconnect are  
inputs to a four-input LUT as shown in Figure 2–7. The Quartus II Compiler  
automatically selects the carry-in or the data3signal as one of the inputs to the LUT.  
Each LE can use LUT chain connections to drive its combinational output directly to  
the next LE in the LAB. Asynchronous load data for the register comes from the data3  
input of the LE. LEs in normal mode support packed registers.  
Figure 2–7. LE in Normal Mode  
sload  
sclear  
aload  
(LAB Wide) (LAB Wide)  
(LAB Wide)  
Register chain  
connection  
addnsub (LAB Wide)  
ALD/PRE  
(1)  
Row, column, and  
ADATA  
D
Q
DirectLink routing  
data1  
data2  
Row, column, and  
DirectLink routing  
ENA  
CLRN  
data3  
cin (from cout  
of previous LE)  
4-Input  
LUT  
clock (LAB Wide)  
Local routing  
data4  
ena (LAB Wide)  
aclr (LAB Wide)  
LUT chain  
connection  
Register  
chain output  
Register Feedback  
Note to Figure 2–7:  
(1) This signal is only allowed in normal mode if the LE is after an adder/subtractor chain.  
Dynamic Arithmetic Mode  
The dynamic arithmetic mode is ideal for implementing adders, counters,  
accumulators, wide parity functions, and comparators. A LE in dynamic arithmetic  
mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first  
two 2-input LUTs compute two summations based on a possible carry-in of 1 or 0; the  
other two LUTs generate carry outputs for the two chains of the carry-select circuitry.  
As shown in Figure 2–8, the LAB carry-in signal selects either the carry-in0or  
carry-in1chain. The selected chain’s logic level in turn determines which parallel  
sum is generated as a combinational or registered output. For example, when  
implementing an adder, the sum output is the selection of two possible calculated  
sums:  
data1 + data2 + carry-in0  
or  
data1 + data2 + carry-in1  
MAX V Device Handbook  
December 2010 Altera Corporation  
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