Chapter 7: User Flash Memory in MAX V Devices
7–33
Software Support for UFM Block
RDSR (Read Status Register)
The content of the status register can be read by issuing RDSR. After RDSRis received,
the interface outputs the content of the status register through the SOport. Although
the four most significant bits (Bit 7 to Bit 4) do not hold valuable information, all eight
bits in the status register will output through the SOport. This allows future
compatibility when Bit 7 to Bit 4 have new meaning in the status register. During the
internal program cycle in the UFM, RDSRis the only valid opcode recognized by the
interface (therefore, the status register can be read at any time), and nRDYis the only
valid status bit. Other status bits are frozen and remain unchanged until the internal
program cycle is ended. RDSRis issued through the following sequence, as shown in
Figure 7–30:
1. nCSis pulled low.
2. Opcode 00000101is transmitted into the interface.
3. SIignores incoming signals; SOoutputs the content of the status register, Bit7first
and Bit0last.
4. If nCSis kept low, repeat step 3.
5. nCSis pulled back to high to terminate the transmission.
Figure 7–30. RDSR Operation Sequence
nCS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
8-bit
Instruction
05H
MSB
MSB
High Impedance
SO
Status Register Out
MSB
MSB
January 2011 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
