Chapter 7: User Flash Memory in MAX V Devices
7–15
Software Support for UFM Block
Acknowledge
Acknowledged data transfer is a requirement of I2C. The master must generate a clock
pulse to signify the acknowledge bit. The transmitter releases the SDA line (high)
during the acknowledge clock pulse.
The receiver (slave) must pull the SDA line low during the acknowledge clock pulse
so that SDA remains a stable low during the clock high period, indicating positive
acknowledgement from the receiver. If the receiver pulls the SDA line high during the
acknowledge clock pulse, the receiver sends a not-acknowledge condition indicating
that it is unable to process the last byte of data. If the receiver is busy (for example,
executing an internally-timed erase or write operation), it will not acknowledge any
new data transfer. Figure 7–10 shows the acknowledge condition on the I2C bus.
Figure 7–10. Acknowledge on the I2C Bus
Data Output
By Transmitter
Not Acknowledge
Acknowledge
Data Output
By Receiver
SCL From
Master
S
Clock Pulse For
Acknowledgement
Start Condition
Device Addressing
After the start condition, the master sends the address of the particular slave device it
is requesting. The four most significant bits (MSBs) of the 8-bit slave address are
usually fixed while the next three significant bits (A2, A1, A0) are device address bits
that define which device the master is accessing. The last bit of the slave address
specifies whether a read or write operation is to be performed. When this bit is set to
1, a read operation is selected. When this bit is set to 0, a write operation is selected.
The four MSBs of the slave address (A6, A5, A4, A3) are programmable and can be
defined on page 3 of the ALTUFM MegaWizard Plug-In Manager. The default value
for these four MSBs is 1010. The next three significant bits are defined using the three
A2, A1, A0 input ports of the ALTUFM_I2C megafunction. You can connect these ports
to input pins in the design file and connect them to switches on the board. The other
option is to connect them to VCC and GND primitives in the design file, which
conserves pins. Figure 7–11 shows the slave address bits.
January 2011 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
