Switching Characteristics
Page 29
Table 25. PLL Specifications for Cyclone V Devices (Part 3 of 3)
Symbol
tDRIFT
Parameter
Min
Typ
—
Max
10
Unit
Frequency drift after PFDENA is disabled for a duration of
—
%
100 µs
dKBIT
Bit number of Delta Sigma Modulator (DSM)
Numerator of fraction
8
24
32
Bits
—
kVALUE
128
8388608 2147483648
5.96 0.023
fRES
Resolution of VCO frequency (fINPFD =100 MHz)
390625
Hz
Notes to Table 25:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(2) The VCO frequency reported by the Quartus II software takes into consideration the VCO post-scale counter
value of 2, the frequency reported can be lower than the fVCO specification.
K value. Therefore, if the counter K has a
(3) This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
(5) FREF is fIN/N, specification applies when N = 1.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the
intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different
measurement method and are available in Table 31 on page 1–33.
(7) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(8) High bandwidth PLL settings are not supported in external feedback mode.
(9) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 31 on page 1–33.
(10) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.
(11) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz.
DSP Block Specifications
Table 26 lists the Cyclone V DSP block performance specifications.
Table 26. DSP Block Performance Specifications for Cyclone V Devices
Performance
Mode
Unit
–C6
–C7, –I7
–C8, –A7
Modes using One DSP Block
Independent 9 x 9 Multiplication
Independent 18 x 19 Multiplication
Independent 18 x 18 Multiplication
Independent 27 x 27 Multiplication
Independent 18 x 25 Multiplication
Independent 20 x 24 Multiplication
Two 18 x 19 Multiplier Adder Mode
18 x 18 Multiplier Added Summed with 36-bit Input
Modes using Two DSP Blocks
340
287
287
250
310
310
310
310
300
250
250
200
250
250
250
250
260
200
200
160
200
200
200
200
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Complex 18 x 19 multiplication
310
250
200
MHz
July 2014 Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL ]
