Switching Characteristics
Page 19
Table 20. Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices (Part 4 of 4)
Transceiver
Transceiver
Transceiver
Speed Grade 7
Speed Grade 5 (1)
Speed Grade 6
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Transceiver-FPGA Fabric Interface
Interface speed
—
25
25
—
—
187.5
25
25
—
—
187.5
25
25
—
—
163.84 MHz
156.25 MHz
(single-width mode)
Interface speed
—
163.84
163.84
(double-width mode)
Notes to Table 20:
(1) Transceiver Speed Grade 5 covers specifications for Cyclone V GT and ST devices.
(2) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(3) The reference clock frequency must be ≥ 307.2 MHz to be fully compliance to CPRI transmit jitter specification at 6.144 Gbps. For more information about
CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(4) The transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10-12
.
(5) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT FPGA systems which require full compliance
to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices
under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(6) Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at
4.9152 Gbps (Cyclone V GT and ST devices) and 6.144 Gbps (Cyclone V GT devices only). For more information about the maximum full duplex channels
recommended in Cyclone V GT devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
(7) The maximum supported clock frequency is 100 MHz if the PCIe hard IP block is enabled or 125 MHz if the PCIe hard IP block is not enabled.
(8) The device cannot tolerate prolonged operation at this absolute maximum.
(9) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the
Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(10) tLTR is the time required for the receive clock data recovery (CDR) to lock to the input reference clock frequency after coming out of reset.
(11) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
(12) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is
functioning in the manual mode.
(13) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR
is functioning in the manual mode.
(14) The rate matcher supports only up to 300 parts per million (ppm).
(15) The AC coupled VICM is 650 mV for PCIe mode only.
(16) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
(17) The Quartus II software allows AC gain setting = 3 for design with data rate between 614 Mbps and 1.25 Gbps only.
July 2014 Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL ]
